Issued Patents 2020
Showing 25 most recent of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879390 | Boosted vertical field-effect transistor | Injo Ok, Soon-Cheon Seo, Seyoung Kim | 2020-12-29 |
| 10879352 | Vertically stacked nFETs and pFETs with gate-all-around structure | Jingyun Zhang, Takashi Ando, Pouya Hashemi, Alexander Reznicek | 2020-12-29 |
| 10879311 | Vertical transport Fin field effect transistors combined with resistive memory structures | Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi | 2020-12-29 |
| 10840145 | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | Juntao Li, Kangguo Cheng, Shogo Mochizuki | 2020-11-17 |
| 10840052 | Planar gate-insulated vacuum channel transistor | Injo Ok, Soon-Cheon Seo, Seyoung Kim | 2020-11-17 |
| 10840349 | Formation of air gap spacers for reducing parasitic capacitance | Kangguo Cheng, Peng Xu, Heng Wu | 2020-11-17 |
| 10833168 | Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures | Soon-Cheon Seo, Injo Ok | 2020-11-10 |
| 10832962 | Formation of an air gap spacer using sacrificial spacer layer | Kangguo Cheng, Peng Xu | 2020-11-10 |
| 10832969 | Single-fin CMOS transistors with embedded and cladded source/drain structures | Xin Miao, Shogo Mochizuki, Hemanth Jagannathan | 2020-11-10 |
| 10832955 | Methods and structures for forming uniform fins when using hardmask patterns | Peng Xu, Kangguo Cheng, Yann Mignot | 2020-11-10 |
| 10832970 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Kangguo Cheng, Juntao Li, Peng Xu | 2020-11-10 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Brent A. Anderson, Junli Wang, Kangguo Cheng, Hemanth Jagannathan | 2020-11-10 |
| 10832960 | Quadruple gate dielectric for gate-all-around transistors | Jingyun Zhang, Takashi Ando | 2020-11-10 |
| 10833200 | Techniques for forming vertical transport FET having gate stacks with a combination of work function metals | Kangguo Cheng, Juntao Li | 2020-11-10 |
| 10832941 | Airgap isolation for backend embedded memory stack pillar arrays | Soon-Cheon Seo, Injo Ok, Alexander Reznicek | 2020-11-10 |
| 10833172 | Gate stack reliability in vertical transport field effect transistors | Christopher J. Waskiewicz, Miaomiao Wang, Hemanth Jagannathan | 2020-11-10 |
| 10825916 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Alexander Reznicek, Christopher J. Waskiewicz | 2020-11-03 |
| 10825736 | Nanosheet with selective dipole diffusion into high-k | Jingyun Zhang, Takashi Ando, Alexander Reznicek | 2020-11-03 |
| 10818756 | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2020-10-27 |
| 10818753 | VTFET having a V-shaped groove at the top junction region | Alexander Reznicek, Injo Ok, Soon-Cheon Seo | 2020-10-27 |
| 10811413 | Multi-threshold vertical FETs with common gates | Takashi Ando, Reinaldo Vega, Hari V. Mallela, Li-Wen Hung | 2020-10-20 |
| 10804165 | Source and drain isolation for CMOS nanosheet with one block mask | Soon-Cheon Seo, Injo Ok | 2020-10-13 |
| 10804410 | Bottom channel isolation in nanosheet transistors | Robin Hsin Kuo Chao, Chun Wing Yeung, Jingyun Zhang | 2020-10-13 |
| 10790199 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Ruqiang Bao, Hemanth Jagannathan, Richard Southwick | 2020-09-29 |
| 10790357 | VFET with channel profile control using selective GE oxidation and drive-out | Pouya Hashemi, Takashi Ando, Alexander Reznicek, Jingyun Zhang | 2020-09-29 |