HW

Heng Wu

IBM: 16 patents #227 of 11,274Top 3%
ET Elpis Technologies: 2 patents #7 of 95Top 8%
TE Tessera: 1 patents #44 of 99Top 45%
Overall (2020): #2,362 of 565,922Top 1%
19
Patents 2020

Issued Patents 2020

Patent #TitleCo-InventorsDate
10840349 Formation of air gap spacers for reducing parasitic capacitance Kangguo Cheng, Peng Xu, Choonghyun Lee 2020-11-17
10833081 Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET) Chen Zhang, Joshua M. Rubin, Tenko Yamashita 2020-11-10
10833079 Dual transport orientation for stacked vertical transport field-effect transistors Tenko Yamashita, Chen Zhang, Kangguo Cheng 2020-11-10
10811322 Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure Kangguo Cheng, Chen Zhang, Tenko Yamashita 2020-10-20
10804368 Semiconductor device having two-part spacer Ruqiang Bao, Junli Wang, Dechao Guo, Ernest Y. Wu 2020-10-13
10797163 Leakage control for gate-all-around field-effect transistor devices Lan Yu, Ruqiang Bao, Junli Wang, Dechao Guo 2020-10-06
10777647 Fin-type FET with low source or drain contact resistance Kangguo Cheng, Juntao Li, Peng Xu 2020-09-15
10727323 Three-dimensional (3D) tunneling field-effect transistor (FET) Juntao Li, Kangguo Cheng, Peng Xu 2020-07-28
10727315 Nanosheet transistor Kangguo Cheng, Juntao Li, Peng Xu 2020-07-28
10699959 Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors Kangguo Cheng, Xuefeng Liu, Peng Xu 2020-06-30
10692772 Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors Kangguo Cheng, Xuefeng Liu, Peng Xu 2020-06-23
10693007 Wrapped contacts with enhanced area Kangguo Cheng, Zuoguang Liu, Peng Xu 2020-06-23
10692778 Gate-all-around FETs having uniform threshold voltage Ruqiang Bao, Dechao Guo, Junli Wang 2020-06-23
10608096 Formation of air gap spacers for reducing parasitic capacitance Kangguo Cheng, Peng Xu, Choonghyun Lee 2020-03-31
10573561 Formation of stacked nanosheet semiconductor devices Kangguo Cheng, Juntao Li, Peng Xu 2020-02-25
10564125 Self-aligned nanotips with tapered vertical sidewalls Juntao Li, Kangguo Cheng, Peng Xu 2020-02-18
10566246 Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices Kangguo Cheng, Junli Wang, Zuoguang Liu 2020-02-18
10559491 Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap Kangguo Cheng, Zuoguang Liu, Sebastian Naczas, Peng Xu 2020-02-11
10529850 Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile Chun Wing Yeung, Choonghyun Lee, Jingyun Zhang, Robin Hsin Kuo Chao 2020-01-07