Issued Patents 2020
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879311 | Vertical transport Fin field effect transistors combined with resistive memory structures | Choonghyun Lee, Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2020-12-29 |
| 10879352 | Vertically stacked nFETs and pFETs with gate-all-around structure | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek | 2020-12-29 |
| 10832960 | Quadruple gate dielectric for gate-all-around transistors | Takashi Ando, Choonghyun Lee | 2020-11-10 |
| 10825736 | Nanosheet with selective dipole diffusion into high-k | Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2020-11-03 |
| 10804410 | Bottom channel isolation in nanosheet transistors | Robin Hsin Kuo Chao, Choonghyun Lee, Chun Wing Yeung | 2020-10-13 |
| 10790357 | VFET with channel profile control using selective GE oxidation and drive-out | Pouya Hashemi, Takashi Ando, Alexander Reznicek, Choonghyun Lee | 2020-09-29 |
| 10763177 | I/O device for gate-all-around transistors | Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi | 2020-09-01 |
| 10756216 | Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity | Xin Miao, Alexander Reznicek, Choonghyun Lee | 2020-08-25 |
| 10756176 | Stacked nanosheet technology with uniform Vth control | Pouya Hashemi, Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2020-08-25 |
| 10748819 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Choonghyun Lee, Sanghoon Shin, Pouya Hashemi, Alexander Reznicek | 2020-08-18 |
| 10748994 | Vertically stacked nFET and pFET with dual work function | Alexander Reznicek, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-08-18 |
| 10741660 | Nanosheet single gate (SG) and extra gate (EG) field effect transistor (FET) co-integration | Nicolas Loubet, Siva Kanakasabapathy, Kangguo Cheng | 2020-08-11 |
| 10734447 | Field-effect transistor unit cells for neural networks with differential weights | Takashi Ando, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee | 2020-08-04 |
| 10734479 | FinFET CMOS with asymmetric gate threshold voltage | Alexander Reznicek, Choonghyun Lee, Takashi Ando, Pouya Hashemi | 2020-08-04 |
| 10734286 | Multiple dielectrics for gate-all-around transistors | Takashi Ando, Alexander Reznicek, Choonghyun Lee, Pouya Hashemi | 2020-08-04 |
| 10720502 | Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek | 2020-07-21 |
| 10707304 | Vertically stacked nFET and pFET with dual work function | Alexander Reznicek, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-07-07 |
| 10700064 | Multi-threshold voltage gate-all-around field-effect transistor devices with common gates | Takashi Ando, Choonghyun Lee | 2020-06-30 |
| 10692866 | Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages | Takashi Ando, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek | 2020-06-23 |
| 10672891 | Stacked gate all around MOSFET with symmetric inner spacer formed via sacrificial pure Si anchors | Pouya Hashemi, Takashi Ando, Choonghyun Lee | 2020-06-02 |
| 10664966 | Anomaly detection using image-based physical characterization | Dechao Guo, Liying Jiang, Derrick Liu, Huimei Zhou | 2020-05-26 |
| 10658462 | Vertically stacked dual channel nanosheet devices | Choonghyun Lee, Pouya Hashemi, Takashi Ando, Alexander Reznicek | 2020-05-19 |
| 10643899 | Gate stack optimization for wide and narrow nanosheet transistor devices | Takashi Ando, Choonghyun Lee | 2020-05-05 |
| 10636874 | External resistance reduction with embedded bottom source/drain for vertical transport FET | Choonghyun Lee, Reinaldo Vega, Miaomiao Wang | 2020-04-28 |
| 10622466 | Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness | Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-04-14 |