Issued Patents 2020
Showing 1–25 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879132 | Combination of tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors | — | 2020-12-29 |
| 10872962 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh | 2020-12-22 |
| 10854753 | Uniform fin dimensions using fin cut hardmask | Peng Xu | 2020-12-01 |
| 10847639 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2020-11-24 |
| 10840147 | Fin cut forming single and double diffusion breaks | Juntao Li, Junli Wang, Ruilong Xie | 2020-11-17 |
| 10840329 | Nanosheet transistor having improved bottom isolation | Ruilong Xie, Chun-Chen Yeh | 2020-11-17 |
| 10840351 | Transistor with airgap spacer and tight gate pitch | — | 2020-11-17 |
| 10840145 | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2020-11-17 |
| 10840148 | One-time programmable device compatible with vertical transistor processing | Juntao Li, Ruilong Xie, Chanro Park | 2020-11-17 |
| 10840381 | Nanosheet and nanowire MOSFET with sharp source/drain junction | Josephine B. Chang, Michael A. Guillorn, Xin Miao | 2020-11-17 |
| 10840349 | Formation of air gap spacers for reducing parasitic capacitance | Peng Xu, Choonghyun Lee, Heng Wu | 2020-11-17 |
| 10832943 | Gate contact over active region with self-aligned source/drain contact | Su Chen Fan, Cheng Chi, Ruilong Xie | 2020-11-10 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James J. Kelly +1 more | 2020-11-10 |
| 10832970 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Choonghyun Lee, Juntao Li, Peng Xu | 2020-11-10 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Brent A. Anderson, Junli Wang, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10832954 | Forming a reliable wrap-around contact without source/drain sacrificial regions | Julien Frougier, Ruilong Xie | 2020-11-10 |
| 10833157 | iFinFET | Juntao Li, Chen Zhang, Xin Miao | 2020-11-10 |
| 10833158 | III-V segmented finFET free of wafer bonding | Xin Miao, Chen Zhang, Wenyu Xu | 2020-11-10 |
| 10833079 | Dual transport orientation for stacked vertical transport field-effect transistors | Tenko Yamashita, Chen Zhang, Heng Wu | 2020-11-10 |
| 10833175 | Formation of dislocation-free SiGe finFET using porous silicon | Stephen W. Bedell, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana | 2020-11-10 |
| 10832907 | Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance | Yi Song, Zhenxing Bi | 2020-11-10 |
| 10833165 | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance | Juntao Li, Son V. Nguyen, Chanro Park | 2020-11-10 |
| 10832127 | Three-dimensional integration of neurosynaptic chips | Qing Cao, Zhengwen Li, Fei Liu | 2020-11-10 |
| 10832947 | Fully aligned via formation without metal recessing | Chanro Park, Ruilong Xie, Juntao Li | 2020-11-10 |
| 10832962 | Formation of an air gap spacer using sacrificial spacer layer | Peng Xu, Choonghyun Lee | 2020-11-10 |