Issued Patents 2020
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840381 | Nanosheet and nanowire MOSFET with sharp source/drain junction | Josephine B. Chang, Kangguo Cheng, Xin Miao | 2020-11-17 |
| 10804278 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-10-13 |
| 10741641 | Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices | Nicolas Loubet | 2020-08-11 |
| 10706200 | Generative adversarial networks for generating physical design layout patterns of integrated multi-layers | Jing Sha, Martin Burkhardt, Derren N. Dunn | 2020-07-07 |
| 10699955 | Techniques for creating a local interconnect using a SOI wafer | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2020-06-30 |
| 10699055 | Generative adversarial networks for generating physical design layout patterns | Jing Sha, Martin Burkhardt, Derren N. Dunn | 2020-06-30 |
| 10680061 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Isaac Lauer, Xin Miao | 2020-06-09 |
| 10658461 | Nanowire with sacrificial top wire | Josephine B. Chang, Bruce B. Doris, Isaac Lauer, Xin Miao | 2020-05-19 |
| 10650111 | Electrical mask validation | Daniel A. Corliss, Derren N. Dunn, Shawn P. Fetterolf | 2020-05-12 |
| 10621301 | Coordinates-based variational autoencoder for generating synthetic via layout patterns | Jing Sha, Derren N. Dunn | 2020-04-14 |
| 10621302 | Classification and localization of hotspots in integrated physical design layouts | Jing Sha, Dongbing Shao, Martin Burkhardt | 2020-04-14 |
| 10615281 | Semiconductor device including wrap around contact and method of forming the semiconductor device | Nicolas Loubet | 2020-04-07 |
| 10606980 | Method and recording medium of reducing chemoepitaxy directed self-assembled defects | Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, HsinYu Tsai | 2020-03-31 |
| 10606975 | Coordinates-based generative adversarial networks for generating synthetic physical design layout patterns | Jing Sha, Derren N. Dunn | 2020-03-31 |
| 10600680 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Chung-Hsun Lin, HsinYu Tsai | 2020-03-24 |
| 10599807 | Automatic generation of via patterns with coordinate-based recurrent neural network (RNN) | Jing Sha, Derren N. Dunn | 2020-03-24 |
| 10592635 | Generating synthetic layout patterns by feedforward neural network based variational autoencoders | Jing Sha, Derren N. Dunn | 2020-03-17 |
| 10586854 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Terence B. Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita | 2020-03-10 |
| 10580858 | Preventing threshold voltage variability in stacked nanosheets | Nicolas Loubet | 2020-03-03 |
| 10573714 | Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs | Josephine B. Chang, Isaac Lauer, Xin Miao | 2020-02-25 |
| 10559670 | Nanosheet field effect transistors with partial inside spacers | Terence B. Hook, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla | 2020-02-11 |