Issued Patents 2020
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10833238 | Wirebond cross-talk reduction for quantum computing chips | Markus Brink | 2020-11-10 |
| 10833146 | Horizontal-trench capacitor | Zheng Xu, Ruqiang Bao, Zhenxing Bi | 2020-11-10 |
| 10831976 | Predicting local layout effects in circuit design patterns | Jing Sha, Yufei Wu, Zheng Xu | 2020-11-10 |
| 10831973 | Semiconductor process modeling to enable skip via in place and route flow | Zheng Xu, Lawrence A. Clevenger | 2020-11-10 |
| 10796069 | Bump connection placement in quantum devices in a flip chip configuration | Markus Brink | 2020-10-06 |
| 10790271 | Perpendicular stacked field-effect transistor device | Zheng Xu, Chen Zhang, Ruqiang Bao | 2020-09-29 |
| 10706205 | Detecting hotspots in physical design layout patterns utilizing hotspot detection model with data augmentation | Jing Sha, Kafai Lai | 2020-07-07 |
| 10678971 | Space exploration with Bayesian inference | Jing Sha, Derren N. Dunn | 2020-06-09 |
| 10657212 | Application- or algorithm-specific quantum circuit design | Martin O. Sandberg, Markus Brink | 2020-05-19 |
| 10628544 | Optimizing integrated circuit designs based on interactions between multiple integration design rules | Dureseti Chidambarrao, Jason D. Hibbeler, Steven Zebertavage | 2020-04-21 |
| 10621295 | Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield | Jinning Liu, Jing Sha, Robert C. Wong | 2020-04-14 |
| 10621302 | Classification and localization of hotspots in integrated physical design layouts | Jing Sha, Martin Burkhardt, Michael A. Guillorn | 2020-04-14 |
| 10599805 | Superconducting quantum circuits layout design verification | Markus Brink, Salvatore Bernardo Olivadese, Jerry M. Chow | 2020-03-24 |
| 10592814 | Automatic design flow from schematic to layout for superconducting multi-qubit systems | Markus Brink, Salvatore Bernardo Olivadese, Jerry M. Chow | 2020-03-17 |
| 10592627 | Optimizing integrated circuit designs based on interactions between multiple integration design rules | Dureseti Chidambarrao, Jason D. Hibbeler, Steven Zebertavage | 2020-03-17 |
| 10586012 | Semiconductor process modeling to enable skip via in place and route flow | Zheng Xu, Lawrence A. Clevenger | 2020-03-10 |
| 10585346 | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization | Chieh-Yu Lin, Kehan Tian, Zheng Xu | 2020-03-10 |
| 10573528 | Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic | Fee Li Lie, Robert C. Wong, Yongan Xu | 2020-02-25 |
| 10539881 | Generation of hotspot-containing physical design layout patterns | Jing Sha, Martin Burkhardt, Sean D. Burns | 2020-01-21 |
| 10535994 | Air gap metal tip electrostatic discharge protection | Qianwen Chen, Yang Liu, Zheng Xu | 2020-01-14 |
| 10534258 | Structure design generation for fixing metal tip-to-tip across cell boundary | Geng Han | 2020-01-14 |
| 10527932 | Structure design generation for fixing metal tip-to-tip across cell boundary | Geng Han | 2020-01-07 |
| 10530150 | Air gap metal tip electrostatic discharge protection | Qianwen Chen, Yang Liu, Zheng Xu | 2020-01-07 |