| 10879375 |
Gate tie-down enablement with inner spacer |
Andre P. Labonte, Lars Liebmann, Sanjay C. Mehta |
2020-12-29 |
| 10833173 |
Low-resistance top contact on VTFET |
Christopher J. Waskiewicz, Hari Prasad Amanapu, Hemanth Jagannathan |
2020-11-10 |
| 10832961 |
Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor |
Ruilong Xie, Veeraraghavan S. Basker, Andre P. Labonte, Chanro Park |
2020-11-10 |
| 10832943 |
Gate contact over active region with self-aligned source/drain contact |
Cheng Chi, Kangguo Cheng, Ruilong Xie |
2020-11-10 |
| 10818548 |
Method and structure for cost effective enhanced self-aligned contacts |
Kafai Lai, Chih-Chao Yang, Yongan Xu |
2020-10-27 |
| 10804148 |
Buried contact to provide reduced VFET feature-to-feature tolerance requirements |
Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie |
2020-10-13 |
| 10796957 |
Buried contact to provide reduced VFET feature-to-feature tolerance requirements |
Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie |
2020-10-06 |
| 10727317 |
Bottom contact formation for vertical transistor devices |
Ekmini Anuja De Silva, Sivananda K. Kanakasabapathy |
2020-07-28 |
| 10685876 |
Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability |
Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala |
2020-06-16 |
| 10658190 |
Extreme ultraviolet lithography patterning with directional deposition |
Yongan Xu, Ekmini Anuja De Silva, Yann Mignot |
2020-05-19 |
| 10622458 |
Self-aligned contact for vertical field effect transistor |
Brent A. Anderson, Steven R. Bentley, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie |
2020-04-14 |
| 10615027 |
Stack viabar structures |
Hsueh-Chung Chen, Yann Mignot, James J. Kelly, Terence B. Hook |
2020-04-07 |
