Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10804148 | Buried contact to provide reduced VFET feature-to-feature tolerance requirements | Su Chen Fan, Robert C. Wong, Ruilong Xie | 2020-10-13 |
| 10796957 | Buried contact to provide reduced VFET feature-to-feature tolerance requirements | Su Chen Fan, Robert C. Wong, Ruilong Xie | 2020-10-06 |
| 10629698 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, John R. Sporre, Sean Teehan | 2020-04-21 |
| 10600868 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Nicole Saulnier | 2020-03-24 |
| 10586733 | Multi-level air gap formation in dual-damascene structure | Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen | 2020-03-10 |