Issued Patents 2020
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10833267 | Structure and method to form phase change memory cell with self- align top electrode contact | Injo Ok, Myung-Hee Na, Balasubramanian Pranatharthiharan | 2020-11-10 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2020-11-10 |
| 10803933 | Self-aligned high density and size adjustable phase change memory | Injo Ok, Myung-Hee Na, Balasubramanian Pranatharthiharan | 2020-10-13 |
| 10741756 | Phase change memory with a patterning scheme for tantalum nitride and silicon nitride layers | Injo Ok, Iqbal Rashid Saraf, Kevin W. Brew | 2020-08-11 |
| 10725454 | Mask process aware calibration using mask pattern fidelity inspections | Ravi K. Bonam, Michael M. Crouse, Derren N. Dunn | 2020-07-28 |
| 10622250 | Dielectric gap fill evaluation for integrated circuits | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve +3 more | 2020-04-14 |
| 10600868 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey C. Shearer | 2020-03-24 |
| 10573808 | Phase change memory with a dielectric bi-layer | Iqbal Rashid Saraf, Kevin W. Brew, Injo Ok, Robert L. Bruce | 2020-02-25 |
| 10546774 | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more | 2020-01-28 |
| 10529569 | Self aligned pattern formation post spacer etchback in tight pitch configurations | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy +2 more | 2020-01-07 |