Issued Patents 2020
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10790393 | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning | Andrew M. Greene, Hong He, Gauri Karve, Eric R. Miller, Pietro Montanini | 2020-09-29 |
| 10741647 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Fee Li Lie, Tenko Yamashita | 2020-08-11 |
| 10727317 | Bottom contact formation for vertical transistor devices | Su Chen Fan, Ekmini Anuja De Silva | 2020-07-28 |
| 10707083 | High aspect ratio gates | Kangguo Cheng, Peng Xu | 2020-07-07 |
| 10629495 | Low undercut N-P work function metal patterning in nanosheet replacement metal gate process | Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Romain Lallement, Ruqiang Bao +1 more | 2020-04-21 |
| 10622352 | Fin cut to prevent replacement gate collapse on STI | Andrew M. Greene, Balasubramanian Pranatharthiharan, John R. Sporre | 2020-04-14 |
| 10615278 | Preventing strained fin relaxation | Kangguo Cheng, Bruce B. Doris, Hong He, Gauri Karve, Juntao Li +3 more | 2020-04-07 |
| 10613438 | Self-aligned patterning methods which implement directed self-assembly | Sean D. Burns, Kafai Lai, Chi-Chun Liu, Kristin Schmidt, Ankit Vora | 2020-04-07 |
| 10600884 | Additive core subtractive liner for metal cut etch processes | Ruqiang Bao, Kisup Chung, Andrew M. Greene, David L. Rath, Indira Seshadri +1 more | 2020-03-24 |
| 10593802 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Kangguo Cheng, Dechao Guo, Peng Xu | 2020-03-17 |
| 10593679 | Static random access memory (SRAM) density scaling by using middle of line (MOL) flow | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang | 2020-03-17 |
| 10546774 | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Yann Mignot, Christopher J. Penny +2 more | 2020-01-28 |
| 10535662 | Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture | Kevin K. Chan, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert +1 more | 2020-01-14 |
| 10529569 | Self aligned pattern formation post spacer etchback in tight pitch configurations | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Christopher J. Penny +2 more | 2020-01-07 |