Issued Patents 2020
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10832952 | Selective recessing to form a fully aligned via | Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee | 2020-11-10 |
| 10833257 | Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts | Ashim Dutta, John C. Arnold, Chih-Chao Yang | 2020-11-10 |
| 10833149 | Capacitors | Veeraraghavan S. Basker, Kangguo Cheng, Christopher J. Penny, Junli Wang | 2020-11-10 |
| 10830841 | Magnetic tunnel junction performance monitoring based on magnetic field coupling | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Lawrence A. Clevenger, James H. Stathis | 2020-11-10 |
| 10825890 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2020-11-03 |
| 10825891 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2020-11-03 |
| 10796833 | Magnetic tunnel junction with low series resistance | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Lawrence A. Clevenger, James H. Stathis | 2020-10-06 |
| 10777735 | Contact via structures | Chih-Chao Yang, Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Nathan P. Marchack | 2020-09-15 |
| 10770511 | Structures and methods for embedded magnetic random access memory (MRAM) fabrication | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo | 2020-09-08 |
| 10748893 | Electrostatic discharge devices and methods of manufacture | Huiming Bu, Junjun Li, Tenko Yamashita | 2020-08-18 |
| 10746782 | Accelerated wafer testing using non-destructive and localized stress | Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo, James H. Stathis | 2020-08-18 |
| 10739397 | Accelerated wafer testing using non-destructive and localized stress | Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo, James H. Stathis | 2020-08-11 |
| 10720567 | Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield | Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo | 2020-07-21 |
| 10714681 | Embedded magnetic tunnel junction pillar having reduced height and uniform contact area | Michael Rizzolo, Cornelius Brown Peethala | 2020-07-14 |
| 10714683 | Multilayer hardmask for high performance MRAM devices | Michael Rizzolo, Daniel C. Edelstein, Kisup Chung, Isabel Cristina Chu, John C. Arnold | 2020-07-14 |
| 10707128 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2020-07-07 |
| 10699962 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2020-06-30 |
| 10692989 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2020-06-23 |
| 10692925 | Dielectric fill for memory pillar elements | Michael Rizzolo, Isabel Cristina Chu, Chih-Chao Yang, Son V. Nguyen | 2020-06-23 |
| 10686124 | Contact via structures | Chih-Chao Yang, Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Nathan P. Marchack | 2020-06-16 |
| 10685915 | Via contact resistance control | Chih-Chao Yang | 2020-06-16 |
| 10680169 | Multilayer hardmask for high performance MRAM devices | Michael Rizzolo, Daniel C. Edelstein, Kisup Chung, Isabel Cristina Chu, John C. Arnold | 2020-06-09 |
| 10672887 | Vertical FET with shaped spacer to reduce parasitic capacitance | Junli Wang, Kangguo Cheng, Veeraraghavan S. Basker | 2020-06-02 |
| 10658589 | Alignment through topography on intermediate component for memory device patterning | Hao Tang, Michael Rizzolo, Injo Ok | 2020-05-19 |
| 10636706 | Selective recessing to form a fully aligned via | Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee | 2020-04-28 |