Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879375 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2020-12-29 |
| 10872809 | Contact structures for integrated circuit products | Ruilong Xie, Balasubramanian S. Pranatharthi Haran, Veeraraghavan S. Basker | 2020-12-22 |
| 10796056 | Optimizing library cells with wiring in metallization layers | Gregory A. Northrop, Lionel Riviere-Cazaux, Kai Sun, Norihito Nakamoto | 2020-10-06 |
| 10727308 | Gate contact structure for a transistor | Ruilong Xie, Hao Tang, Cheng Chi, Daniel Chanemougame, Mark V. Raymond | 2020-07-28 |
| 10720391 | Method of forming a buried interconnect and the resulting devices | Bipul C. Paul, Ruilong Xie | 2020-07-21 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven R. Soss, Hui Zang +1 more | 2020-06-30 |
| 10685874 | Self-aligned cuts in an interconnect structure | Ruilong Xie, Hui Zang, Lei Sun, Daniel Chanemougame, Guillaume Bouche | 2020-06-16 |
| 10651284 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Heimanu Niebojewski +3 more | 2020-05-12 |
| 10586762 | Interrupted small block shape | Guillaume Bouche | 2020-03-10 |