Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

US Patent 10879375 · Granted Dec 29, 2020

Estimated economic value: $5,669,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertical field effect transistor with minimal contact to gate erosion2025
Semiconductor device having hybrid middle of line contacts2025
Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)2025
Stacked field effect transistor structure with independent gate control between 2025
Bottom contact with self-aligned spacer for stacked semiconductor devices2025
Field effect transistor with backside source/drain2025
Method and structure of forming sidewall contact for stacked FET2025
Tapered device for lateral gate all around devices2025
Electronic devices with a low dielectric constant2025
Replacement buried power rail in backside power delivery2025
Self-aligned method for vertical recess for 3D device integration2025
Bottom contact for stacked GAA FET2025