Issued Patents 2020
Showing 26–50 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10833073 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Juntao Li | 2020-11-10 |
| 10832956 | Method and structure for forming transistors with high aspect ratio gate without patterning collapse | — | 2020-11-10 |
| 10833175 | Formation of dislocation-free SiGe finFET using porous silicon | Stephen W. Bedell, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana | 2020-11-10 |
| 10833165 | Asymmetric air spacer gate-controlled device with reduced parasitic capacitance | Juntao Li, Son V. Nguyen, Chanro Park | 2020-11-10 |
| 10832947 | Fully aligned via formation without metal recessing | Chanro Park, Ruilong Xie, Juntao Li | 2020-11-10 |
| 10832970 | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor | Choonghyun Lee, Juntao Li, Peng Xu | 2020-11-10 |
| 10832962 | Formation of an air gap spacer using sacrificial spacer layer | Peng Xu, Choonghyun Lee | 2020-11-10 |
| 10833147 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodoras E. Standaert, Junli Wang | 2020-11-10 |
| 10833204 | Multiple width nanosheet devices | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2020-11-10 |
| 10832950 | Interconnect with high quality ultra-low-k dielectric | — | 2020-11-10 |
| 10832907 | Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance | Yi Song, Zhenxing Bi | 2020-11-10 |
| 10832127 | Three-dimensional integration of neurosynaptic chips | Qing Cao, Zhengwen Li, Fei Liu | 2020-11-10 |
| 10832916 | Self-aligned gate isolation with asymmetric cut placement | Ruilong Xie, Carl Radens, Veeraraghavan S. Basker | 2020-11-10 |
| 10825689 | Method of fabricating semiconductor fins by enhancing oxidation of sacrificial mandrels sidewalls through angled ion beam exposure | — | 2020-11-03 |
| 10825890 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-11-03 |
| 10825891 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-11-03 |
| 10825917 | Bulk FinFET with fin channel height uniformity and isolation | — | 2020-11-03 |
| 10818663 | Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition | Fee Li Lie, Eric R. Miller, Sean Teehan | 2020-10-27 |
| 10818668 | Metal trench capacitor and improved isolation and methods of manufacture | Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang | 2020-10-27 |
| 10818756 | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-10-27 |
| 10818776 | Nanosheet transistor with optimized junction and cladding detectivity control | Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-10-27 |
| 10818791 | Nanosheet transistor with stable structure | — | 2020-10-27 |
| 10818559 | Formation of multi-segment channel transistor devices | — | 2020-10-27 |
| 10811495 | Vertical field effect transistor with uniform gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2020-10-20 |
| 10811322 | Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure | Heng Wu, Chen Zhang, Tenko Yamashita | 2020-10-20 |