Issued Patents 2019
Showing 26–50 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10446654 | Gate contact structures and self-aligned contact process | Hui Zang | 2019-10-15 |
| 10446399 | Hard mask layer to reduce loss of isolation material during dummy gate removal | Min Gyu Sung, Chanro Park, Hoon Kim | 2019-10-15 |
| 10439031 | Integration of vertical-transport transistors and electrical fuses | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2019-10-08 |
| 10431651 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, John H. Zhang | 2019-10-01 |
| 10431663 | Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure | Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier | 2019-10-01 |
| 10431682 | Vertical vacuum channel transistor | Qing Liu, Chun-Chen Yeh | 2019-10-01 |
| 10424657 | Tri-gate FinFET device | Andreas Knorr | 2019-09-24 |
| 10418484 | Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods | Lars Liebmann, Edward J. Nowak, Julien Frougier, Jia Zeng | 2019-09-17 |
| 10418449 | Circuits based on complementary field-effect transistors | Bipul C. Paul, Puneet Harischandra Suvarna | 2019-09-17 |
| 10410929 | Multiple gate length device with self-aligned top junction | Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti | 2019-09-10 |
| 10410933 | Replacement metal gate patterning for nanosheet devices | Chanro Park, Min Gyu Sung, Hoon Kim, Hui Zang, Guowei Xu | 2019-09-10 |
| 10411010 | Tall single-fin FIN-type field effect transistor structures and methods | Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel G. Cave | 2019-09-10 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Tenko Yamashita, Chun-Chen Yeh | 2019-08-27 |
| 10395939 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Cheng Chi, Fee Li Lie, Chi-Chun Liu | 2019-08-27 |
| 10395995 | Dual liner silicide | Balasubramanian Pranatharthiharan, Chun-Chen Yeh | 2019-08-27 |
| 10388770 | Gate and source/drain contact structures positioned above an active region of a transistor device | Chanro Park, Christopher M. Prindle | 2019-08-20 |
| 10388732 | Nanosheet field-effect transistors including a two-dimensional semiconducting material | Julien Frougier, Nicolas Loubet, Kangguo Cheng, Juntao Li | 2019-08-20 |
| 10388747 | Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure | Christopher M. Prindle, Emilie Bourjot, Laertis Economikos | 2019-08-20 |
| 10388731 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2019-08-20 |
| 10388754 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2019-08-20 |
| 10388654 | Methods of forming a gate-to-source/drain contact structure | Judson R. Holt, George R. Mulfinger, Timothy J. McArdle, Thomas Merbeth, Omur Isil Aydin | 2019-08-20 |
| 10388602 | Local interconnect structure including non-eroded contact via trenches | Su Chen Fan, Vimal Kamineni, Andre P. Labonte | 2019-08-20 |
| 10388760 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2019-08-20 |
| 10388652 | Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same | Yongiun Shi, Lei Sun, Laertis Economikos, Lars Liebmann, Chanro Park +4 more | 2019-08-20 |
| 10381273 | Vertically stacked multi-channel transistor structure | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2019-08-13 |