Issued Patents 2019
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522655 | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI | Ryan Sporer, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel | 2019-12-31 |
| 10396078 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park +1 more | 2019-08-27 |
| 10388654 | Methods of forming a gate-to-source/drain contact structure | Judson R. Holt, Timothy J. McArdle, Thomas Merbeth, Omur Isil Aydin, Ruilong Xie | 2019-08-20 |
| 10326007 | Post gate silicon germanium channel condensation and method for producing the same | Ryan Sporer, Timothy J. McArdle, Judson R. Holt | 2019-06-18 |
| 10236343 | Strain retention semiconductor member for channel SiGe layer of pFET | Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child | 2019-03-19 |
| 10217660 | Technique for patterning active regions of transistor elements in a late manufacturing stage | Ryan Sporer | 2019-02-26 |