Issued Patents 2019
Showing 51–75 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10438855 | Dual channel FinFETs having uniform fin heights | Zhenxing Bi, Peng Xu, Jie Yang | 2019-10-08 |
| 10431557 | Secure semiconductor chip by piezoelectricity | Qing Cao, Fei Liu, Zhengwen Li | 2019-10-01 |
| 10431667 | Vertical field effect transistors with uniform threshold voltage | Xin Miao, Heng Wu, Peng Xu | 2019-10-01 |
| 10431659 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Xin Miao, Wenyu Xu, Chen Zhang | 2019-10-01 |
| 10431651 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Cheng Chi, Ruilong Xie, John H. Zhang | 2019-10-01 |
| 10431646 | Electronic devices having spiral conductive structures | Peng Xu, Xuefeng Liu, Chi-Chun Liu, Yongan Xu | 2019-10-01 |
| 10431495 | Semiconductor device with local connection | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2019-10-01 |
| 10431660 | Self-limiting fin spike removal | Choonghyun Lee, Juntao Li, Peng Xu | 2019-10-01 |
| 10424639 | Nanosheet transistor with high-mobility channel | Xin Miao, Wenyu Xu, Chen Zhang | 2019-09-24 |
| 10424653 | Vertical transport field effect transistor on silicon with defined junctions | Chen Zhang, Xin Miao, Wenyu Xu | 2019-09-24 |
| 10424651 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Julien Frougier, Nicolas Loubet | 2019-09-24 |
| 10422746 | Nanoscale surface with nanoscale features formed using diffusion at a liner-semiconductor interface | Juntao Li, Qing Cao | 2019-09-24 |
| 10424663 | Super long channel device within VFET architecture | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-09-24 |
| 10424585 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-09-24 |
| 10424482 | Methods and structures for forming a tight pitch structure | Peng Xu, Choonghyun Lee, Juntao Li | 2019-09-24 |
| 10418280 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-09-17 |
| 10418463 | Silicon germanium alloy fins with reduced defects | Hong He, Juntao Li | 2019-09-17 |
| 10418277 | Air gap spacer formation for nano-scale semiconductor devices | Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen +2 more | 2019-09-17 |
| 10410927 | Method and structure for forming transistors with high aspect ratio gate without patterning collapse | — | 2019-09-10 |
| 10410928 | Homogeneous densification of fill layers for controlled reveal of vertical fins | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2019-09-10 |
| 10411094 | Method and structure for forming silicon germanium FinFET | Peng Xu, Juntao Li, Heng Wu | 2019-09-10 |
| 10411106 | Transistor with air spacer and self-aligned contact | Xin Miao, Peng Xu, Chen Zhang | 2019-09-10 |
| 10411114 | Air gap spacer with wrap-around etch stop layer under gate spacer | Chen Zhang, Xin Miao, Wenyu Xu, Peng Xu | 2019-09-10 |
| 10411128 | Strained fin channel devices | Junli Wang, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2019-09-10 |
| 10403772 | Electrical and optical via connections on a same chip | Juntao Li, Chengwen Pei, Geng Wang, Joseph Ervin | 2019-09-03 |