Issued Patents 2005
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979903 | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | Steven C. Avanzino, Pin-Chin Connie Wang | 2005-12-27 |
| 6972254 | Manufacturing a conformal atomic liner layer in an integrated circuit interconnect | Sergey Lopatin | 2005-12-06 |
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Ming-Ren Lin, Eric N. Paton, Haihong Wang, Qi Xiang, Jung-Suk Goo | 2005-11-08 |
| 6955997 | Laser thermal annealing method for forming semiconductor low-k dielectric layer | Arvind Halliyal | 2005-10-18 |
| 6951220 | Method of decontaminating equipment | Farzad Arasnia, Paul R. Besser, Qi Xiang | 2005-10-04 |
| 6933219 | Tightly spaced gate formation through damascene process | Emmanuil H. Lingunis, Krishnashree Achuthan, Cyrus E. Tabery, Jean Y. Yang | 2005-08-23 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Qi Xiang, Ming-Ren Lin, Eric N. Paton, Haihong Wang | 2005-08-02 |
| 6905971 | Treatment of dielectric material to enhance etch rate | Cyrus E. Tabery, Chih-Yuh Yang, William G. En, Joong S. Jeon, Ming-Ren Lin | 2005-06-14 |
| 6903007 | Process for forming bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing | David K. Foote | 2005-06-07 |
| 6900121 | Laser thermal annealing to eliminate oxide voiding | Arvind Halliyal, Dawn Hopper | 2005-05-31 |
| 6900488 | Multi-cell organic memory element and methods of operating and fabricating | Sergey Lopatin, Mark S. Chang, Patrick K. Cheung | 2005-05-31 |
| 6897144 | Cu capping layer deposition with improved integrated circuit reliability | Paul R. Besser, Larry Zhao | 2005-05-24 |
| 6894342 | Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control | Angela T. Hui, Ning Cheng, Jaeyong Park, Jean Y. Yang, Hirokazu Tokuno +2 more | 2005-05-17 |
| 6893929 | Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends | Qi Xiang, Ming-Ren Lin, Haihong Wang | 2005-05-17 |
| 6893910 | One step deposition method for high-k dielectric and metal gate electrode | Christy Mei-Chu Woo, Paul R. Besser, James Pan, Jinsong Yin | 2005-05-17 |
| 6884681 | Method of manufacturing a semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2005-04-26 |
| 6878592 | Selective epitaxy to improve silicidation | Paul R. Besser, Qi Xiang, Eric N. Paton | 2005-04-12 |
| 6875694 | Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials | Robert A. Huertas, Hieu Pham | 2005-04-05 |
| 6861350 | Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode | Christy Mei-Chu Woo, Jinsong Yin, James Pan, Paul R. Besser | 2005-03-01 |
| 6858503 | Depletion to avoid cross contamination | Ming-Ren Lin, Paul R. Besser, Qi Xiang, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6849925 | Preparation of composite high-K/standard-K dielectrics for semiconductor devices | Arvind Halliyal, Joong S. Jeon, Robert B. Ogle | 2005-02-01 |