Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6969886 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Inkuk Kang, Tazrien Kamal +1 more | 2005-11-29 |
| 6955965 | Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device | Arvind Halliyal, Tazrien Kamal, Hidehiko Shiraiwa | 2005-10-18 |
| 6949481 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device | Arvind Halliyal, Fred Cheung, Rinji Sugino, Hidehiko Shiraiwa, Tazrien Kamal | 2005-09-27 |
| 6933219 | Tightly spaced gate formation through damascene process | Emmanuil H. Lingunis, Krishnashree Achuthan, Minh Van Ngo, Cyrus E. Tabery | 2005-08-23 |
| 6927145 | Bitline hard mask spacer flow for memory cell scaling | Mark T. Ramsbey, Jaeyong Park, Tazrien Kamal, Emmanuil H. Lingunis | 2005-08-09 |
| 6897533 | Multi-bit silicon nitride charge-trapping non-volatile memory cell | Yider Wu | 2005-05-24 |
| 6884681 | Method of manufacturing a semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Hidehiko Shiraiwa +1 more | 2005-04-26 |
| 6869844 | Method and structure for protecting NROM devices from induced charge damage during device fabrication | Zhizheng Liu, Yider Wu | 2005-03-22 |
| 6855608 | Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance | Mark T. Ramsbey, Mark Randolph, Hiroyuki Kinoshita, Cyrus E. Tabery, Jeff P. Erhardt +3 more | 2005-02-15 |