Issued Patents 2005
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6969654 | Flash NVROM devices with UV charge immunity | Tuan Pham, Jeffrey A. Shields, Angela T. Hui, Dawn Hopper | 2005-11-29 |
| 6962849 | Hard mask spacer for sublithographic bitline | Tazrien Kamal, Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Ashok M. Khathuria | 2005-11-08 |
| 6958511 | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | Arvind Halliyal, Amir H. Jafarpour, Hidehiko Shiraiwa, Tazrien Kamal, Jaeyong Park | 2005-10-25 |
| 6958272 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell | Emmanuil H. Lingunis, Nga-Ching Wong, Sameer Haddad, Mark Randolph, Ashot Melik-Martirosian +2 more | 2005-10-25 |
| 6927145 | Bitline hard mask spacer flow for memory cell scaling | Jean Y. Yang, Jaeyong Park, Tazrien Kamal, Emmanuil H. Lingunis | 2005-08-09 |
| 6912163 | Memory device having high work function gate and method of erasing same | Wei Zheng, Yun Wu, Hidehiko Shiraiwa, Tazrien Kamal | 2005-06-28 |
| 6900085 | ESD implant following spacer deposition | Michael Fliesler, Mark Randolph, Mimi Qian, Yu Sun | 2005-05-31 |
| 6884681 | Method of manufacturing a semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Minh Van Ngo, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2005-04-26 |
| 6872643 | Implant damage removal by laser thermal annealing | Arvind Halliyal, Nicholas H. Tripsas | 2005-03-29 |
| 6867097 | Method of making a memory cell with polished insulator layer | Robert B. Ogle, Tommy Hsiao, Angela T. Hui, Tuan Pham, Marina V. Plat +1 more | 2005-03-15 |
| 6861307 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas | 2005-03-01 |
| 6855608 | Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance | Mark Randolph, Jean Y. Yang, Hiroyuki Kinoshita, Cyrus E. Tabery, Jeff P. Erhardt +3 more | 2005-02-15 |