Issued Patents 2005
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6967873 | Memory device and method using positive gate stress to recover overerased cell | Darlene Hamilton, Zhizheng Liu, Yi He, Edward Hsia, Kulachet Tanpairoj +2 more | 2005-11-22 |
| 6965143 | Recess channel flash architecture for reduced short channel effect | Wei Zheng | 2005-11-15 |
| 6958272 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell | Emmanuil H. Lingunis, Nga-Ching Wong, Sameer Haddad, Mark T. Ramsbey, Ashot Melik-Martirosian +2 more | 2005-10-25 |
| 6934190 | Ramp source hot-hole programming for trap based non-volatile memory devices | Zengtao T. Liu, Zhizheng Liu, Yi He, Sameer Haddad | 2005-08-23 |
| 6911704 | Memory cell array with staggered local inter-connect structure | Sameer Haddad, Timothy Thurgate, Richard Fastow | 2005-06-28 |
| 6906959 | Method and system for erasing a nitride memory device | Chi Chang, Yi He, Wei Zheng, Edward Franklin Runnion, Zhizheng Liu | 2005-06-14 |
| 6900085 | ESD implant following spacer deposition | Mark T. Ramsbey, Michael Fliesler, Mimi Qian, Yu Sun | 2005-05-31 |
| 6897110 | Method of protecting a memory array from charge damage during fabrication | Yi He, Wei Zheng, Zhizheng Liu, Darlene Hamilton, Ken Tanpairoj | 2005-05-24 |
| 6894932 | Dual cell memory device having a top dielectric stack | Ashot Melik-Martirosian, Sameer Haddad | 2005-05-17 |
| 6868014 | Memory device with reduced operating voltage having dielectric stack | Ashot Melik-Martirosian, Sameer Haddad | 2005-03-15 |
| 6862221 | Memory device having a thin top dielectric and method of erasing same | Ashot Melik-Martirosian, Sameer Haddad | 2005-03-01 |
| 6861307 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2005-03-01 |
| 6855608 | Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance | Mark T. Ramsbey, Jean Y. Yang, Hiroyuki Kinoshita, Cyrus E. Tabery, Jeff P. Erhardt +3 more | 2005-02-15 |