TK

Tazrien Kamal

FA Fasl: 6 patents #1 of 30Top 4%
AM AMD: 5 patents #66 of 906Top 8%
📍 San Jose, CA: #10 of 2,758 inventorsTop 1%
🗺 California: #118 of 26,868 inventorsTop 1%
Overall (2005): #740 of 245,428Top 1%
11
Patents 2005

Issued Patents 2005

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
6969886 ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Inkuk Kang +1 more 2005-11-29
6962849 Hard mask spacer for sublithographic bitline Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Mark T. Ramsbey, Ashok M. Khathuria 2005-11-08
6958511 Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen Arvind Halliyal, Amir H. Jafarpour, Hidehiko Shiraiwa, Mark T. Ramsbey, Jaeyong Park 2005-10-25
6955965 Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device Arvind Halliyal, Hidehiko Shiraiwa, Jean Y. Yang 2005-10-18
6949481 Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device Arvind Halliyal, Fred Cheung, Rinji Sugino, Hidehiko Shiraiwa, Jean Y. Yang 2005-09-27
6927145 Bitline hard mask spacer flow for memory cell scaling Jean Y. Yang, Mark T. Ramsbey, Jaeyong Park, Emmanuil H. Lingunis 2005-08-09
6912163 Memory device having high work function gate and method of erasing same Wei Zheng, Yun Wu, Hidehiko Shiraiwa, Mark T. Ramsbey 2005-06-28
6885590 Memory device having A P+ gate and thin bottom oxide and method of erasing same Wei Zheng, Chi Chang 2005-04-26
6884681 Method of manufacturing a semiconductor memory with deuterated materials Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more 2005-04-26
6872609 Narrow bitline using Safier for mirrorbit Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh 2005-03-29
6855608 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance Mark T. Ramsbey, Mark Randolph, Jean Y. Yang, Hiroyuki Kinoshita, Cyrus E. Tabery +3 more 2005-02-15