Issued Patents 2005
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974983 | Isolated FinFET P-channel/N-channel transistor pair | Wiley Eugene Hill, Shibly S. Ahmed, Bin Yu | 2005-12-13 |
| 6967175 | Damascene gate semiconductor processing with local thinning of channel region | Shibly S. Ahmed, Bin Yu | 2005-11-22 |
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Minh Van Ngo, Ming-Ren Lin, Eric N. Paton, Qi Xiang, Jung-Suk Goo | 2005-11-08 |
| 6958512 | Non-volatile memory device | Yider Wu, Shibly S. Ahmed, Bin Yu | 2005-10-25 |
| 6936882 | Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages | Shibly S. Ahmed, Bin Yu | 2005-08-30 |
| 6933558 | Flash memory device | Wiley Eugene Hill, Yider Wu, Bin Yu | 2005-08-23 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Qi Xiang, Ming-Ren Lin, Minh Van Ngo, Eric N. Paton | 2005-08-02 |
| 6921963 | Narrow fin FinFET | Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Bin Yu | 2005-07-26 |
| 6921709 | Front side seal to prevent germanium outgassing | Eric N. Paton, Qi Xiang | 2005-07-26 |
| 6914277 | Merged FinFET P-channel/N-channel pair | Wiley Eugene Hill, Shibly S. Ahmed, Bin Yu | 2005-07-05 |
| 6911697 | Semiconductor device having a thin fin and raised source/drain areas | Judy Xilin An, Bin Yu | 2005-06-28 |
| 6905923 | Offset spacer process for forming N-type transistors | Eric N. Paton, Qi Xiang | 2005-06-14 |
| 6902991 | Semiconductor device having a thick strained silicon layer and method of its formation | Qi Xiang, Jung-Suk Goo | 2005-06-07 |
| 6897527 | Strained channel FinFET | Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Bin Yu | 2005-05-24 |
| 6894337 | System and method for forming stacked fin structure using metal-induced-crystallization | Shibly S. Ahmed, Bin Yu | 2005-05-17 |
| 6893930 | Fabrication of field effect transistor with shallow junctions using low temperature activation of antimony | Bin Yu | 2005-05-17 |
| 6893929 | Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends | Qi Xiang, Ming-Ren Lin, Minh Van Ngo | 2005-05-17 |
| 6876042 | Additional gate control for a double-gate MOSFET | Bin Yu, Shibly S. Ahmed | 2005-04-05 |
| 6855989 | Damascene finfet gate with selective metal interdiffusion | Shibly S. Ahmed, Ming-Ren Lin, Bin Yu | 2005-02-15 |
| 6855607 | Multi-step chemical mechanical polishing of a gate area in a FinFET | Krishnashree Achuthan, Shibly S. Ahmed, Bin Yu | 2005-02-15 |
| 6852576 | Method for forming structures in finfet devices | Ming-Ren Lin, Bin Yu | 2005-02-08 |
| 6852600 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Qi Xiang | 2005-02-08 |
| 6842048 | Two transistor NOR device | Zoran Krivokapic, Judy Xilin An, Ming-Ren Lin | 2005-01-11 |