Issued Patents 2005
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979635 | Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation | Akif Sultan, Bin Yu | 2005-12-27 |
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Minh Van Ngo, Ming-Ren Lin, Eric N. Paton, Haihong Wang, Jung-Suk Goo | 2005-11-08 |
| 6955969 | Method of growing as a channel region to reduce source/drain junction capacitance | Ihsan Djomehri, Jung-Suk Goo, Srinath Krishnan, Witold P. Maszara, James Pan | 2005-10-18 |
| 6951220 | Method of decontaminating equipment | Farzad Arasnia, Paul R. Besser, Minh Van Ngo | 2005-10-04 |
| 6943087 | Semiconductor on insulator MOSFET having strained silicon channel | Jung-Suk Goo, James Pan, Ming-Ren Lin | 2005-09-13 |
| 6936516 | Replacement gate strained silicon finFET process | Jung-Suk Goo, James Pan | 2005-08-30 |
| 6936506 | Strained-silicon devices with different silicon thicknesses | James F. Buller, Derick J. Wristers, Bin Yu | 2005-08-30 |
| 6929992 | Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift | Ihsan Djomehri, Jung-Suk Goo, James Pan | 2005-08-16 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Ming-Ren Lin, Minh Van Ngo, Eric N. Paton, Haihong Wang | 2005-08-02 |
| 6921709 | Front side seal to prevent germanium outgassing | Eric N. Paton, Haihong Wang | 2005-07-26 |
| 6905923 | Offset spacer process for forming N-type transistors | Eric N. Paton, Haihong Wang | 2005-06-14 |
| 6902977 | Method for forming polysilicon gate on high-k dielectric and related structure | George Jonathan Kluth, Joong S. Jeon, Huicai Zhong | 2005-06-07 |
| 6902966 | Low-temperature post-dopant activation process | Bin Yu, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2005-06-07 |
| 6902991 | Semiconductor device having a thick strained silicon layer and method of its formation | Jung-Suk Goo, Haihong Wang | 2005-06-07 |
| 6900143 | Strained silicon MOSFETs having improved thermal dissipation | James Pan, Jung-Suk Goo | 2005-05-31 |
| 6897122 | Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges | — | 2005-05-24 |
| 6893929 | Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends | Ming-Ren Lin, Minh Van Ngo, Haihong Wang | 2005-05-17 |
| 6878592 | Selective epitaxy to improve silicidation | Paul R. Besser, Minh Van Ngo, Eric N. Paton | 2005-04-12 |
| 6872613 | Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure | Huicai Zhong, Jung-Suk Goo, Allison Holbrook, Joong S. Jeon, George Jonathan Kluth | 2005-03-29 |
| 6867080 | Polysilicon tilting to prevent geometry effects during laser thermal annealing | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Bin Yu | 2005-03-15 |
| 6867428 | Strained silicon NMOS having silicon source/drain extensions and method for its fabrication | Paul R. Besser, Eric N. Paton | 2005-03-15 |
| 6858503 | Depletion to avoid cross contamination | Minh Van Ngo, Ming-Ren Lin, Paul R. Besser, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6855982 | Self aligned double gate transistor having a strained channel region and process therefor | James Pan, Ming-Ren Lin | 2005-02-15 |
| 6852600 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Haihong Wang | 2005-02-08 |
| 6849527 | Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and methods of their formation | — | 2005-02-01 |