Issued Patents 2005
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6958271 | Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor | Ning Cheng, Christy Mein Chu Woo | 2005-10-25 |
| 6955969 | Method of growing as a channel region to reduce source/drain junction capacitance | Ihsan Djomehri, Jung-Suk Goo, Srinath Krishnan, Witold P. Maszara, Qi Xiang | 2005-10-18 |
| 6943087 | Semiconductor on insulator MOSFET having strained silicon channel | Qi Xiang, Jung-Suk Goo, Ming-Ren Lin | 2005-09-13 |
| 6936516 | Replacement gate strained silicon finFET process | Jung-Suk Goo, Qi Xiang | 2005-08-30 |
| 6929992 | Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift | Ihsan Djomehri, Qi Xiang, Jung-Suk Goo | 2005-08-16 |
| 6900143 | Strained silicon MOSFETs having improved thermal dissipation | Jung-Suk Goo, Qi Xiang | 2005-05-31 |
| 6893910 | One step deposition method for high-k dielectric and metal gate electrode | Christy Mei-Chu Woo, Paul R. Besser, Minh Van Ngo, Jinsong Yin | 2005-05-17 |
| 6881277 | Method of processing selected surfaces in a semiconductor process chamber based on a temperature differential between surfaces | — | 2005-04-19 |
| 6864163 | Fabrication of dual work-function metal gate structure for complementary field effect transistors | Allen S. Yu | 2005-03-08 |
| 6861350 | Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode | Minh Van Ngo, Christy Mei-Chu Woo, Jinsong Yin, Paul R. Besser | 2005-03-01 |
| 6861325 | Methods for fabricating CMOS-compatible lateral bipolar junction transistors | Matthew S. Buynoski | 2005-03-01 |
| 6855982 | Self aligned double gate transistor having a strained channel region and process therefor | Qi Xiang, Ming-Ren Lin | 2005-02-15 |