Issued Patents 2005
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Minh Van Ngo, Eric N. Paton, Haihong Wang, Qi Xiang, Jung-Suk Goo | 2005-11-08 |
| 6958264 | Scribe lane for gettering of contaminants on SOI wafers and gettering method | — | 2005-10-25 |
| 6943087 | Semiconductor on insulator MOSFET having strained silicon channel | Qi Xiang, Jung-Suk Goo, James Pan | 2005-09-13 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Qi Xiang, Minh Van Ngo, Eric N. Paton, Haihong Wang | 2005-08-02 |
| 6905971 | Treatment of dielectric material to enhance etch rate | Cyrus E. Tabery, Chih-Yuh Yang, William G. En, Joong S. Jeon, Minh Van Ngo | 2005-06-14 |
| 6893929 | Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends | Qi Xiang, Minh Van Ngo, Haihong Wang | 2005-05-17 |
| 6858503 | Depletion to avoid cross contamination | Minh Van Ngo, Paul R. Besser, Qi Xiang, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6855989 | Damascene finfet gate with selective metal interdiffusion | Haihong Wang, Shibly S. Ahmed, Bin Yu | 2005-02-15 |
| 6855982 | Self aligned double gate transistor having a strained channel region and process therefor | Qi Xiang, James Pan | 2005-02-15 |
| 6852576 | Method for forming structures in finfet devices | Haihong Wang, Bin Yu | 2005-02-08 |
| 6842048 | Two transistor NOR device | Zoran Krivokapic, Judy Xilin An, Haihong Wang | 2005-01-11 |