Issued Patents 2003
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670241 | Semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2003-12-30 |
| 6664187 | Laser thermal annealing for Cu seedlayer enhancement | Minh Quoc Tran | 2003-12-16 |
| 6660634 | Method of forming reliable capped copper interconnects | Shekhar Pramanick, Takeshi Nogami | 2003-12-09 |
| 6660621 | Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation | Paul R. Besser | 2003-12-09 |
| 6661067 | Nitrogen-plasma treatment for reduced nickel silicide bridging | Christy Mei-Chu Woo, Paul R. Besser, Robert A. Huertas | 2003-12-09 |
| 6657304 | Conformal barrier liner in an integrated circuit interconnect | Christy Mei-Chu Woo, John Sanchez, Steven C. Avanzino | 2003-12-02 |
| 6656763 | Spin on polymers for organic memory devices | Jane V. Oglesby, Christopher F. Lyons, Ramkumar Subramanian, Angela T. Hui, Suzette K. Pangrle | 2003-12-02 |
| 6653190 | Flash memory with controlled wordline width | Jean Y. Yang, Kouros Ghandehari, Tazrien Kamal, Mark T. Ramsbey, Dawn Hopper +2 more | 2003-11-25 |
| 6645882 | Preparation of composite high-K/standard-K dielectrics for semiconductor devices | Arvind Halliyal, Joong S. Jeon, Robert B. Ogle | 2003-11-11 |
| 6645853 | Interconnects with improved barrier layer adhesion | Dawn Hopper | 2003-11-11 |
| 6642145 | Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | Steven C. Avanzino, Pin-Chin Connie Wang | 2003-11-04 |
| 6642619 | System and method for adhesion improvement at an interface between fluorine doped silicon oxide and tantalum | Dawn Hopper, Jeremy I. Martin | 2003-11-04 |
| 6638861 | Method of eliminating voids in W plugs | Eric N. Paton | 2003-10-28 |
| 6627973 | Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device | Robert A. Huertas, Lu You, King Wai Kelwin Ko, Pei-Yuan Gao | 2003-09-30 |
| 6617215 | Memory wordline hard mask | Arvind Halliyal, Tazrien Kamal, Mark T. Ramsbey, Jeffrey A. Shields, Jean Y. Yang +3 more | 2003-09-09 |
| 6613657 | BPSG, SA-CVD liner/P-HDP gap fill | Dawn Hopper, Wenmei Li, Kelwin Ko, Kuo-Tung Chang, Tyagamohan Gottipati | 2003-09-02 |
| 6605848 | Semiconductor device with metal gate electrode and silicon oxynitride spacer | Arvind Halliyal | 2003-08-12 |
| 6605513 | Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing | Eric N. Paton, Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski +4 more | 2003-08-12 |
| 6602754 | Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer | George Jonathan Kluth, Paul R. Besser | 2003-08-05 |
| 6599766 | Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer | Cyrus E. Tabery, Chih-Yuh Yang | 2003-07-29 |
| 6599827 | Methods of forming capped copper interconnects with improved electromigration resistance | Steven C. Avanzino, Amit P. Marathe, Hartmut Ruelke | 2003-07-29 |
| 6596631 | Method of forming copper interconnect capping layers with improved interface and adhesion | Hartmut Ruelke, Lothar Mergili, Joerg Hohage, Lu You, Robert A. Huertas +1 more | 2003-07-22 |
| 6593632 | Interconnect methodology employing a low dielectric constant etch stop layer | Steven C. Avanzino, Angela T. Hui, Chun Jiang, Hamid Partovi | 2003-07-15 |
| 6593237 | Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects | Christy Mei-Chu Woo | 2003-07-15 |
| 6586333 | Integrated plasma treatment and nickel deposition and tool for performing same | Christy Mei-Chu Woo | 2003-07-01 |