Issued Patents 2003
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6653735 | CVD silicon carbide layer as a BARC and hard mask for gate patterning | Douglas J. Bonser, Pei-Yuan Gao, Lu You | 2003-11-25 |
| 6653231 | Process for reducing the critical dimensions of integrated circuit device features | Uzodinma Okoroanyanwu, Jeffrey A. Shields | 2003-11-25 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer | Matthew S. Buynoski, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu | 2003-11-11 |
| 6630288 | Process for forming sub-lithographic photoresist features by modification of the photoresist surface | Jeffrey A. Shields, Uzodinma Okoroanyanwu | 2003-10-07 |
| 6606738 | Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology | Scott A. Bell, Marina V. Plat, Amada Wilkison | 2003-08-12 |
| 6599766 | Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer | Cyrus E. Tabery, Minh Van Ngo | 2003-07-29 |
| 6589709 | Process for preventing deformation of patterned photoresist features | Uzodinma Okoroanyanwu, Jeffrey A. Shields | 2003-07-08 |
| 6579809 | In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric | Cyrus E. Tabery | 2003-06-17 |
| 6566230 | Shallow trench isolation spacer for weff improvement | Harpreet Sachar, Unsoon Kim, Mark S. Chang, Jayendra D. Bhakta | 2003-05-20 |
| 6563183 | Gate array with multiple dielectric properties and method for forming same | William G. En, Arvind Halliyal, Minh-Ren Lin, Minh Van Ngo, Cyrus E. Tabery | 2003-05-13 |
| 6544885 | Polished hard mask process for conductor layer patterning | Khanh B. Nguyen, Harry J. Levinson, Christopher F. Lyons, Scott A. Bell, Fei Wang | 2003-04-08 |
| 6514871 | Gate etch process with extended CD trim capability | Scott A. Bell | 2003-02-04 |