Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670691 | Shallow trench isolation fill process | Harpreet Sachar, Jack F. Thomas | 2003-12-30 |
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Yider Wu, Yu Sun, Michael K. Templeton, Angela T. Hui, Chi Chang | 2003-12-16 |
| 6610577 | Self-aligned polysilicon polish | Jack F. Thomas, Krishnashree Achuthan | 2003-08-26 |
| 6607925 | Hard mask removal process including isolation dielectric refill | Dawn Hopper, Yider Wu, Krishnashree Achuthan | 2003-08-19 |
| 6566230 | Shallow trench isolation spacer for weff improvement | Harpreet Sachar, Mark S. Chang, Chih-Yuh Yang, Jayendra D. Bhakta | 2003-05-20 |
| 6555867 | Flash memory gate coupling using HSG polysilicon | — | 2003-04-29 |
| 6548855 | Non-volatile memory dielectric as charge pump dielectric | Mark T. Ramsbey, Arvind Halliyal, Kuo-Tung Chang, Nicholas H. Tripsas, Wei Zheng | 2003-04-15 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Mark S. Chang, Yider Wu, Chi Chang, Angela T. Hui, Yu Sun | 2003-01-21 |