Issued Patents 2003
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6649511 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects | Amit P. Marathe | 2003-11-18 |
| 6613646 | Methods for reduced trench isolation step height | Kashmir Sahota | 2003-09-02 |
| 6610577 | Self-aligned polysilicon polish | Jack F. Thomas, Unsoon Kim | 2003-08-26 |
| 6607925 | Hard mask removal process including isolation dielectric refill | Unsoon Kim, Dawn Hopper, Yider Wu | 2003-08-19 |
| 6605517 | Method for minimizing nitride residue on a silicon wafer | Jayendra D. Bhakta, Angela T. Hui | 2003-08-12 |
| 6569747 | Methods for trench isolation with reduced step height | Kashmir Sahota | 2003-05-27 |
| 6559546 | Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure | Sergey Lopatin | 2003-05-06 |