Issued Patents 2003
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670265 | Low K dielectic etch in high density plasma etcher | Fei Wang, James Kai | 2003-12-30 |
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Unsoon Kim, Yider Wu, Yu Sun, Michael K. Templeton, Chi Chang | 2003-12-16 |
| 6664180 | Method of forming smaller trench line width using a spacer hard mask | Bhanwar Singh | 2003-12-16 |
| 6656763 | Spin on polymers for organic memory devices | Jane V. Oglesby, Christopher F. Lyons, Ramkumar Subramanian, Minh Van Ngo, Suzette K. Pangrle | 2003-12-02 |
| 6653190 | Flash memory with controlled wordline width | Jean Y. Yang, Kouros Ghandehari, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey +2 more | 2003-11-25 |
| 6642148 | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist | Kouros Ghandehari, Emmanuil H. Lingunis, Mark S. Chang, Scott A. Bell, Jusuke Ogura | 2003-11-04 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation | Tuan Pham, Richard J. Huang, Mark T. Ramsbey, Lu You | 2003-10-21 |
| 6617215 | Memory wordline hard mask | Arvind Halliyal, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields +3 more | 2003-09-09 |
| 6605517 | Method for minimizing nitride residue on a silicon wafer | Jayendra D. Bhakta, Krishnashree Achuthan | 2003-08-12 |
| 6593632 | Interconnect methodology employing a low dielectric constant etch stop layer | Steven C. Avanzino, Minh Van Ngo, Chun Jiang, Hamid Partovi | 2003-07-15 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2003-07-08 |
| 6583009 | Innovative narrow gate formation for floating gate flash technology | Kelwin Ko, Hiroyuki Kinoshita, Sameer Haddad, Yu Sun | 2003-06-24 |
| 6573172 | Methods for improving carrier mobility of PMOS and NMOS devices | William G. En, Minh Van Ngo | 2003-06-03 |
| 6573140 | Process for making a dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Kiyoshi Izumi, Masaru Yano, Hideki Komori, Tuan Pham | 2003-06-03 |
| 6548334 | Capping layer | Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2003-04-15 |
| 6528398 | Thinning of trench and line or contact spacing by use of dual layer photoresist | Kouros Ghandehari, Bhanwar Singh | 2003-03-04 |
| 6514867 | Method of creating narrow trench lines using hard mask | Bhanwar Singh | 2003-02-04 |
| 6514874 | Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features | James Yu, Bhanwar Singh | 2003-02-04 |
| 6514868 | Method of creating a smaller contact using hard mask | Bhanwar Singh | 2003-02-04 |
| 6514849 | Method of forming smaller contact size using a spacer hard mask | Bhanwar Singh | 2003-02-04 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Unsoon Kim, Mark S. Chang, Yider Wu, Chi Chang, Yu Sun | 2003-01-21 |
| 6506683 | In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers | YongZhong Hu | 2003-01-14 |