Issued Patents 2003
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation | Angela T. Hui, Richard J. Huang, Mark T. Ramsbey, Lu You | 2003-10-21 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Mark T. Ramsbey, Yu Sun, Chi Chang | 2003-08-12 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2003-07-08 |
| 6573140 | Process for making a dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Kiyoshi Izumi, Masaru Yano, Hideki Komori, Angela T. Hui | 2003-06-03 |
| 6548334 | Capping layer | Mark T. Ramsbey, Sameer Haddad, Angela T. Hui | 2003-04-15 |
| 6537866 | Method of forming narrow insulating spacers for use in reducing minimum component size | Jeffrey A. Shields, Jusuke Ogura, Bharath Rangarajan, Simon S. Chan | 2003-03-25 |
| 6509604 | Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation | Mark T. Ramsbey, Yu Sun, Chi Chang | 2003-01-21 |