Issued Patents 2003
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Unsoon Kim, Yider Wu, Michael K. Templeton, Angela T. Hui, Chi Chang | 2003-12-16 |
| 6645801 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Chi Chang | 2003-11-11 |
| 6630384 | Method of fabricating double densed core gates in sonos flash memory | Michael A. Van Buskirk, Mark T. Ramsbey | 2003-10-07 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Tuan Pham, Mark T. Ramsbey, Chi Chang | 2003-08-12 |
| 6583009 | Innovative narrow gate formation for floating gate flash technology | Angela T. Hui, Kelwin Ko, Hiroyuki Kinoshita, Sameer Haddad | 2003-06-24 |
| 6566736 | Die seal for semiconductor device moisture protection | Hiroyuki Ogawa, Yider Wu | 2003-05-20 |
| 6566194 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Chi Chang | 2003-05-20 |
| 6529412 | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge | Pau-Ling Chen, Michael A. Van Buskirk | 2003-03-04 |
| 6509229 | Method for forming self-aligned contacts using consumable spacers | Fei Wang, Ramkumar Subramanian | 2003-01-21 |
| 6509604 | Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation | Tuan Pham, Mark T. Ramsbey, Chi Chang | 2003-01-21 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Unsoon Kim, Mark S. Chang, Yider Wu, Chi Chang, Angela T. Hui | 2003-01-21 |