Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6630384 | Method of fabricating double densed core gates in sonos flash memory | Yu Sun, Mark T. Ramsbey | 2003-10-07 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Richard Fastow, Shane Hollmer, Pau-Ling Chen, Masaaki Higashitani | 2003-06-24 |
| 6555436 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2003-04-29 |
| 6549466 | Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Narbeh Derhacobian, Chi Chang, Daniel Sobek | 2003-04-15 |
| 6541816 | Planar structure for non-volatile memory devices | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +2 more | 2003-04-01 |
| 6529412 | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge | Pau-Ling Chen, Yu Sun | 2003-03-04 |
| 6515902 | Method and apparatus for boosting bitlines for low VCC read | Pau-Ling Chen | 2003-02-04 |
| 6510082 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Binh Quang Le, Pau-Ling Chen, Santosh Yachareni, Michael Chung, Kazuhiro Kurihara +1 more | 2003-01-21 |