Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6622230 | Multi-set block erase | Masaru Yano, Michael Chung | 2003-09-16 |
| 6593606 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Pau-Ling Chen, Richard Fastow | 2003-07-15 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Richard Fastow, Pau-Ling Chen, Michael A. Van Buskirk, Masaaki Higashitani | 2003-06-24 |
| 6545912 | Erase verify mode to evaluate negative Vt's | Joseph G. Pawletko, Pau-Ling Chen | 2003-04-08 |
| 6538270 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Pau-Ling Chen, Richard Fastow | 2003-03-25 |
| 6525966 | Method and apparatus for adjusting on-chip current reference for EEPROM sensing | Joseph G. Pawletko, Binh Quang Le | 2003-02-25 |
| 6510082 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Binh Quang Le, Pau-Ling Chen, Michael A. Van Buskirk, Santosh Yachareni, Michael Chung +1 more | 2003-01-21 |
| 6504757 | Double boosting scheme for NAND to improve program inhibit characteristics | Pau-Ling Chen, Quang Binh | 2003-01-07 |