Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6643177 | Method for improving read margin in a flash memory device | Binh Quang Le | 2003-11-04 |
| 6622201 | Chained array of sequential access memories enabling continuous read | Michael VanBuskirk | 2003-09-16 |
| 6593606 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Richard Fastow | 2003-07-15 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Richard Fastow, Shane Hollmer, Michael A. Van Buskirk, Masaaki Higashitani | 2003-06-24 |
| 6545912 | Erase verify mode to evaluate negative Vt's | Joseph G. Pawletko, Shane Hollmer | 2003-04-08 |
| 6538270 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Richard Fastow | 2003-03-25 |
| 6529412 | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge | Michael A. Van Buskirk, Yu Sun | 2003-03-04 |
| 6515902 | Method and apparatus for boosting bitlines for low VCC read | Michael A. Van Buskirk | 2003-02-04 |
| 6510082 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Binh Quang Le, Michael A. Van Buskirk, Santosh Yachareni, Michael Chung, Kazuhiro Kurihara +1 more | 2003-01-21 |
| 6504757 | Double boosting scheme for NAND to improve program inhibit characteristics | Shane Hollmer, Quang Binh | 2003-01-07 |