Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6654285 | Method of matching core cell and reference cell source resistances | Jiang Li, Lee Cleveland | 2003-11-25 |
| 6646914 | Flash memory array architecture having staggered metal lines | Sameer Haddad | 2003-11-11 |
| 6593606 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Pau-Ling Chen | 2003-07-15 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Shane Hollmer, Pau-Ling Chen, Michael A. Van Buskirk, Masaaki Higashitani | 2003-06-24 |
| 6570211 | 2Bit/cell architecture for floating gate flash memory product and associated method | Yue-Song He, Zheng Wei | 2003-05-27 |
| 6541338 | Low defect density process for deep sub-0.18 &mgr;m flash memory technologies | Zhigang Wang, Yue-Song He | 2003-04-01 |
| 6538270 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Pau-Ling Chen | 2003-03-25 |
| 6525959 | NOR array with buried trench source line | — | 2003-02-25 |
| 6525368 | High density flash EEPROM array with source side injection | — | 2003-02-25 |
| 6510085 | Method of channel hot electron programming for short channel NOR flash arrays | Sheunghee Park, Zhigang Wang, Sameer Haddad, Chi Chang | 2003-01-21 |