Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Unsoon Kim, Yider Wu, Yu Sun, Michael K. Templeton, Angela T. Hui | 2003-12-16 |
| 6653189 | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | Sameer Haddad, Yue-Song He, Timothy Thurgate, Mark Randolph, Ngaching Wong | 2003-11-25 |
| 6645801 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun | 2003-11-11 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2003-08-12 |
| 6566194 | Salicided gate for virtual ground arrays | Mark T. Ramsbey, Yu Sun | 2003-05-20 |
| 6549466 | Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Narbeh Derhacobian, Michael A. Van Buskirk, Daniel Sobek | 2003-04-15 |
| 6524914 | Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory | Yue-Song He, Sameer Haddad, Timothy Thurgate | 2003-02-25 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Unsoon Kim, Mark S. Chang, Yider Wu, Angela T. Hui, Yu Sun | 2003-01-21 |
| 6510085 | Method of channel hot electron programming for short channel NOR flash arrays | Richard Fastow, Sheunghee Park, Zhigang Wang, Sameer Haddad | 2003-01-21 |
| 6509604 | Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2003-01-21 |