Issued Patents 2003
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670265 | Low K dielectic etch in high density plasma etcher | James Kai, Angela T. Hui | 2003-12-30 |
| 6664185 | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect | Pin-Chin Connie Wang | 2003-12-16 |
| 6660619 | Dual damascene metal interconnect structure with dielectric studs | Suzette K. Pangrle, Lynne A. Okada | 2003-12-09 |
| 6656830 | Dual damascene with silicon carbide middle etch stop layer/ARC | Ramkumar Subramanian, Dawn Hopper, Lynne A. Okada | 2003-12-02 |
| 6632707 | Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning | Lynne A. Okada, Ramkumar Subramanian, James Kai, Calvin T. Gabriel, Lu You | 2003-10-14 |
| 6610608 | Plasma etching using combination of CHF3 and CH3F | Lynne A. Okada, Calvin T. Gabriel | 2003-08-26 |
| 6603206 | Slot via filled dual damascene interconnect structure without middle etch stop layer | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2003-08-05 |
| 6599839 | Plasma etch process for nonhomogenous film | Calvin T. Gabriel, Lynne A. Okada, Dawn Hopper, Suzette K. Pangrle | 2003-07-29 |
| 6586842 | Dual damascene integration scheme for preventing copper contamination of dielectric layer | Lu You, Christy Mei-Chu Woo | 2003-07-01 |
| 6583046 | Post-treatment of low-k dielectric for prevention of photoresist poisoning | Lynne A. Okada, Calvin T. Gabriel | 2003-06-24 |
| 6577009 | Use of sic for preventing copper contamination of dielectric layer | Lu You, Minh Van Ngo | 2003-06-10 |
| 6562683 | Bit-line oxidation by removing ONO oxide prior to bit-line implant | David K. Foote, Stephen Keetai Park | 2003-05-13 |
| 6544885 | Polished hard mask process for conductor layer patterning | Khanh B. Nguyen, Harry J. Levinson, Christopher F. Lyons, Scott A. Bell, Chih-Yuh Yang | 2003-04-08 |
| 6537881 | Process for fabricating a non-volatile memory device | Bharath Rangarajan, David K. Foote, Steven K. Park | 2003-03-25 |
| 6534397 | Pre-treatment of low-k dielectric for prevention of photoresist poisoning | Lynne A. Okada, Calvin T. Gabriel | 2003-03-18 |
| 6528409 | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration | Sergey Lopatin, Diana M. Schonauer, Steven C. Avanzino | 2003-03-04 |
| 6528390 | Process for fabricating a non-volatile memory device | Hideki Komori, David K. Foote, Bharath Rangarajan | 2003-03-04 |
| 6524947 | Slotted trench dual inlaid structure and method of forming thereof | Ramkumar Subramanian, Todd P. Lukanc | 2003-02-25 |
| 6521524 | Via filled dual damascene structure with middle stop layer and method for making the same | Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel | 2003-02-18 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Pin-Chin Connie Wang, Kashmir Sahota, Steven C. Avanzino, Amit P. Marathe, Matthew S. Buynoski +2 more | 2003-02-11 |
| 6514860 | Integration of organic fill for dual damascene process | Lynne A. Okada, James Kai | 2003-02-04 |
| 6509229 | Method for forming self-aligned contacts using consumable spacers | Ramkumar Subramanian, Yu Sun | 2003-01-21 |