Issued Patents 2003
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664154 | Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes | Srikanteswara Dakshina-Murthy, Philip A. Fisher, Cyrus E. Tabery | 2003-12-16 |
| 6660645 | Process for etching an organic dielectric using a silyated photoresist mask | Todd P. Lukanc, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian | 2003-12-09 |
| 6653190 | Flash memory with controlled wordline width | Jean Y. Yang, Kouros Ghandehari, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey +2 more | 2003-11-25 |
| 6642152 | Method for ultra thin resist linewidth reduction using implantation | Che-Hoo Ng, Anne E. Sanderfer, Christopher Lee Pike | 2003-11-04 |
| 6642148 | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist | Kouros Ghandehari, Emmanuil H. Lingunis, Mark S. Chang, Angela T. Hui, Jusuke Ogura | 2003-11-04 |
| 6635409 | Method of strengthening photoresist to prevent pattern collapse | Christopher F. Lyons, Todd P. Lukanc, Marina V. Plat | 2003-10-21 |
| 6627360 | Carbonization process for an etch mask | Christopher F. Lyons | 2003-09-30 |
| 6620717 | Memory with disposable ARC for wordline formation | Tazrien Kamal, Kouros Ghandehari, Mark T. Ramsbey, Jeffrey A. Shields, Jean Y. Yang | 2003-09-16 |
| 6606738 | Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology | Marina V. Plat, Amada Wilkison, Chih-Yuh Yang | 2003-08-12 |
| 6605514 | Planar finFET patterning using amorphous carbon | Cyrus E. Tabery, Srikanteswara Dakshina-Murthy | 2003-08-12 |
| 6596553 | Method of pinhole decoration and detection | David Lin, Philip A. Fisher, Srikanteswara Dakshina-Murthy | 2003-07-22 |
| 6566214 | Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer | Christopher F. Lyons, Ramkumar Subramanian, Todd P. Lukanc, Marina V. Plat | 2003-05-20 |
| 6563221 | Connection structures for integrated circuits and processes for their formation | Todd P. Lukanc, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian | 2003-05-13 |
| 6548423 | Multilayer anti-reflective coating process for integrated circuit fabrication | Marina V. Plat, Christopher F. Lyons, Todd P. Lukanc | 2003-04-15 |
| 6544885 | Polished hard mask process for conductor layer patterning | Khanh B. Nguyen, Harry J. Levinson, Christopher F. Lyons, Fei Wang, Chih-Yuh Yang | 2003-04-08 |
| 6541360 | Bi-layer trim etch process to form integrated circuit gate structures | Marina V. Plat, Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh | 2003-04-01 |
| 6534418 | Use of silicon containing imaging layer to define sub-resolution gate structures | Marina V. Plat, Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh | 2003-03-18 |
| 6514871 | Gate etch process with extended CD trim capability | Chih-Yuh Yang | 2003-02-04 |