Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6649511 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects | Krishnashree Achuthan | 2003-11-18 |
| 6649034 | Electro-chemical metal alloying for semiconductor manufacturing | Minh Quoc Tran, Pin-Chin Connie Wang | 2003-11-18 |
| 6621290 | Characterization of barrier layers in integrated circuit interconnects | Pin-Chin Connie Wang | 2003-09-16 |
| 6599827 | Methods of forming capped copper interconnects with improved electromigration resistance | Minh Van Ngo, Steven C. Avanzino, Hartmut Ruelke | 2003-07-29 |
| 6599835 | Testing dielectric and barrier layers for integrated circuit interconnects | Christy Mei-Chu Woo | 2003-07-29 |
| 6590288 | Selective deposition in integrated circuit interconnects | Christy Mei-Chu Woo, Pin-Chin Connie Wang | 2003-07-08 |
| 6531780 | Via formation in integrated circuit interconnects | Christy Mei-Chu Woo, Pin-Chin Connie Wang | 2003-03-11 |
| 6531777 | Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP | Christy Mei-Chu Woo | 2003-03-11 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Pin-Chin Connie Wang, Fei Wang, Kashmir Sahota, Steven C. Avanzino, Matthew S. Buynoski +2 more | 2003-02-11 |
| 6506677 | Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance | Steven C. Avanzino, Minh Van Ngo, Hartmut Ruelke | 2003-01-14 |