Issued Patents 2003
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664185 | Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect | Fei Wang | 2003-12-16 |
| 6663787 | Use of ta/tan for preventing copper contamination of low-k dielectric layers | Lu You, Christy Mei-Chu Woo | 2003-12-16 |
| 6657303 | Integrated circuit with low solubility metal-conductor interconnect cap | Steven C. Avanzino | 2003-12-02 |
| 6656836 | Method of performing a two stage anneal in the formation of an alloy interconnect | Paul R. Besser | 2003-12-02 |
| 6649034 | Electro-chemical metal alloying for semiconductor manufacturing | Minh Quoc Tran, Amit P. Marathe | 2003-11-18 |
| 6642145 | Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | Steven C. Avanzino, Minh Van Ngo | 2003-11-04 |
| 6621290 | Characterization of barrier layers in integrated circuit interconnects | Amit P. Marathe | 2003-09-16 |
| 6617176 | METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED | John Sanchez, Christy Mei-Chu Woo, Paul R. Besser | 2003-09-09 |
| 6590288 | Selective deposition in integrated circuit interconnects | Christy Mei-Chu Woo, Amit P. Marathe | 2003-07-08 |
| 6589408 | Non-planar copper alloy target for plasma vapor deposition systems | Paul R. Besser, Sergey Lopatin, Minh Quoc Tran | 2003-07-08 |
| 6573179 | Forming a strong interface between interconnect and encapsulation to minimize electromigration | Lu You | 2003-06-03 |
| 6566248 | Graphoepitaxial conductor cores in integrated circuit interconnects | Minh Quoc Tran | 2003-05-20 |
| 6555909 | Seedless barrier layers in integrated circuits and a method of manufacture therefor | Sergey Lopatin | 2003-04-29 |
| 6548395 | Method of promoting void free copper interconnects | Christy Mei-Chu Woo | 2003-04-15 |
| 6541860 | Barrier-to-seed layer alloying in integrated circuit interconnects | Christy Mei-Chu Woo, Joffre F. Bernard | 2003-04-01 |
| 6534865 | Method of enhanced fill of vias and trenches | Sergey Lopatin | 2003-03-18 |
| 6531780 | Via formation in integrated circuit interconnects | Christy Mei-Chu Woo, Amit P. Marathe | 2003-03-11 |
| 6528412 | Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening | Sergey Lopatin | 2003-03-04 |
| 6525425 | Copper interconnects with improved electromigration resistance and low resistivity | Christy Mei-Chu Woo | 2003-02-25 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Fei Wang, Kashmir Sahota, Steven C. Avanzino, Amit P. Marathe, Matthew S. Buynoski +2 more | 2003-02-11 |
| 6518167 | Method of forming a metal or metal nitride interface layer between silicon nitride and copper | Lu You, Matthew S. Buynoski, Paul R. Besser, Jeremias D. Romero, Minh Quoc Tran | 2003-02-11 |