Issued Patents 2003
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6583051 | Method of manufacturing an amorphized barrier layer for integrated circuit interconnects | Sergey Lopatin, Minh Quoc Tran | 2003-06-24 |
| 6577009 | Use of sic for preventing copper contamination of dielectric layer | Lu You, Fei Wang | 2003-06-10 |
| 6576982 | Use of sion for preventing copper contamination of dielectric layer | Lu You, Dawn Hopper | 2003-06-10 |
| 6576548 | Method of manufacturing a semiconductor device with reliable contacts/vias | Amy C. Tu, Austin Frenkel, Robert J. Chiu, Jeff P. Erhardt | 2003-06-10 |
| 6576545 | Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers | Dawn Hopper, Lu You | 2003-06-10 |
| 6573172 | Methods for improving carrier mobility of PMOS and NMOS devices | William G. En, Angela T. Hui | 2003-06-03 |
| 6569768 | Surface treatment and capping layer process for producing a copper interface in a semiconductor device | Hartmut Ruelke, Joerg Hohage | 2003-05-27 |
| 6566283 | Silane treatment of low dielectric constant materials in semiconductor device manufacturing | Suzette K. Pangrle, Dawn Hopper, Lu You | 2003-05-20 |
| 6566252 | Method for simultaneous deposition and sputtering of TEOS and device thereby formed | Paul R. Besser | 2003-05-20 |
| 6562416 | Method of forming low resistance vias | Robert A. Huertas, Dawn Hopper | 2003-05-13 |
| 6563183 | Gate array with multiple dielectric properties and method for forming same | William G. En, Arvind Halliyal, Minh-Ren Lin, Cyrus E. Tabery, Chih-Yuh Yang | 2003-05-13 |
| 6562718 | Process for forming fully silicided gates | Qi Xiang, Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski +5 more | 2003-05-13 |
| 6555461 | Method of forming low resistance barrier on low k interconnect | Christy Mei-Chu Woo, Suzette K. Pangrle | 2003-04-29 |
| 6548403 | Silicon oxide liner for reduced nickel silicide bridging | Christy Mei-Chu Woo | 2003-04-15 |
| 6545370 | Composite silicon nitride sidewall spacers for reduced nickel silicide bridging | Christy Mei-Chu Woo, Paul R. Besser | 2003-04-08 |
| 6541866 | Cobalt barrier for nickel silicidation of a gate electrode | Jacques Bertrand, Christy Mei-Chu Woo, George Jonathan Kluth | 2003-04-01 |
| 6534869 | Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby | Bryan Tracy, Paul R. Besser | 2003-03-18 |
| 6528884 | Conformal atomic liner layer in an integrated circuit interconnect | Sergey Lopatin | 2003-03-04 |
| 6528432 | H2-or H2/N2-plasma treatment to prevent organic ILD degradation | Dawn Hopper, Robert A. Huertas | 2003-03-04 |
| 6525391 | Nickel silicide process using starved silicon diffusion barrier | Jacques Bertrand | 2003-02-25 |
| 6525428 | Graded low-k middle-etch stop layer for dual-inlaid patterning | Steven C. Avanzino, Christy Mei-Chu Woo, John Sanchez | 2003-02-25 |
| 6521529 | HDP treatment for reduced nickel silicide bridging | Christy Mei-Chu Woo, Ercan Adem, Robert A. Huertas | 2003-02-18 |
| 6515367 | Sub-cap and method of manufacture therefor in integrated circuit capping layers | Joffre F. Bernard, Tim Z. Hossain | 2003-02-04 |
| 6509282 | Silicon-starved PECVD method for metal gate electrode dielectric spacer | Arvind Halliyal | 2003-01-21 |
| 6506677 | Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance | Steven C. Avanzino, Amit P. Marathe, Hartmut Ruelke | 2003-01-14 |