Issued Patents 2003
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6613500 | Reducing resist residue defects in open area on patterned wafer using trim mask | Khoi A. Phan, Bhanwar Singh, Ramkumar Subramanian, Michael K. Templeton | 2003-09-02 |
| 6576548 | Method of manufacturing a semiconductor device with reliable contacts/vias | Amy C. Tu, Minh Van Ngo, Austin Frenkel, Robert J. Chiu | 2003-06-10 |
| 6521501 | Method of forming a CMOS transistor having ultra shallow source and drain regions | Bin Yu, G. Jonathan Kluth | 2003-02-18 |
| 6514859 | Method of salicide formation with a double gate silicide | Eric N. Paton | 2003-02-04 |
| 6513151 | Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation | Khoi A. Phan | 2003-01-28 |