Issued Patents 2003
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6660578 | High-K dielectric having barrier layer for P-doped devices and method of fabrication | Olov Karlsson, Haihong Wang, Bin Yu, Zoran Krivokapic | 2003-12-09 |
| 6656749 | In-situ monitoring during laser thermal annealing | Eric N. Paton, Robert B. Ogle, Bin Yu, Cyrus E. Tabery | 2003-12-02 |
| 6657276 | Shallow trench isolation (STI) region with high-K liner and method of formation | Olov Karlsson, Haihong Wang, Bin Yu, Zoran Krivokapic | 2003-12-02 |
| 6657267 | Semiconductor device and fabrication technique using a high-K liner for spacer etch stop | Olov Karlsson, Haihong Wang, Bin Yu | 2003-12-02 |
| 6657223 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Haihong Wang | 2003-12-02 |
| 6642536 | Hybrid silicon on insulator/bulk strained silicon technology | Akif Sultan | 2003-11-04 |
| 6642590 | Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2003-11-04 |
| 6630720 | Asymmetric semiconductor device having dual work function gate and method of fabrication | Witold P. Maszara, Haihong Wang | 2003-10-07 |
| 6624476 | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | Simon S. Chan, Matthew S. Buynoski | 2003-09-23 |
| 6602781 | Metal silicide gate transistors | Paul R. Besser, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2003-08-05 |
| 6600170 | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS | — | 2003-07-29 |
| 6589866 | Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2003-07-08 |
| 6586808 | Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric | Witold P. Maszara, Haihong Wang | 2003-07-01 |
| 6583012 | Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes | Matthew S. Buynoski, Paul R. Besser | 2003-06-24 |
| 6583488 | Low density, tensile stress reducing material for STI trench fill | — | 2003-06-24 |
| 6562718 | Process for forming fully silicided gates | Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski, John Foster +5 more | 2003-05-13 |
| 6562717 | Semiconductor device having multiple thickness nickel silicide layers | Christy Mei-Chu Woo, George Jonathan Kluth | 2003-05-13 |
| 6555879 | SOI device with metal source/drain and method of fabrication | Zoran Krivokapic, Bin Yu | 2003-04-29 |
| 6555453 | Fully nickel silicided metal gate with shallow junction formed | Christy Mei-Chu Woo, George Jonathan Kluth | 2003-04-29 |
| 6555439 | Partial recrystallization of source/drain region before laser thermal annealing | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Bin Yu | 2003-04-29 |
| 6551888 | Tuning absorption levels during laser thermal annealing | Cyrus E. Tabery, Eric N. Paton, Bin Yu, Robert B. Ogle | 2003-04-22 |
| 6544872 | Dopant implantation processing for improved source/drain interface with metal silicides | Matthew S. Buynoski, George Jonathan Kluth | 2003-04-08 |
| 6534822 | Silicon on insulator field effect transistor with a double Schottky gate structure | Matthew S. Buynoski | 2003-03-18 |
| 6528858 | MOSFETs with differing gate dielectrics and method of formation | Bin Yu, Olov Karlsson, Haihong Wang, Zoran Krivokapic | 2003-03-04 |
| 6528362 | Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Matthew S. Buynoski | 2003-03-04 |