Issued Patents All Time
Showing 126–150 of 355 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10115634 | Semiconductor component having through-silicon vias and method of manufacture | Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang +4 more | 2018-10-30 |
| 10074595 | Self-alignment for redistribution layer | Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai +2 more | 2018-09-11 |
| 10068789 | Method of using a wafer cassette to charge an electrostatic carrier | Yung-Chi Lin, Yu-Liang Lin, Hung-Jung Tu | 2018-09-04 |
| 10062821 | Light-emitting device | Ding-Yuan Chen, Chia-Lin Yu, Chen-Hua Yu | 2018-08-28 |
| 10049928 | Embedded 3D interposer structure | Ying-Ching Shih, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu | 2018-08-14 |
| 10032698 | Interconnection structure with confinement layer | Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu | 2018-07-24 |
| 10020344 | CIS chips and methods for forming the same | Chen-Hua Yu, Jing-Cheng Lin | 2018-07-10 |
| 9997497 | Through silicon via structure | Chen-Hua Yu, Shin-Puu Jeng, Fang Wen Tsai, Chen-Yu Tsai | 2018-06-12 |
| 9997440 | Protection layer for adhesive material at wafer edge | Weng-Jin Wu, Shau-Lin Shue | 2018-06-12 |
| 9978708 | Wafer backside interconnect structure connected to TSVs | Ming-Fa Chen, Shau-Lin Shue | 2018-05-22 |
| 9978607 | Through via structure and method | Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu | 2018-05-22 |
| 9953920 | Interconnect structure and method | Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu +1 more | 2018-04-24 |
| 9922934 | Semiconductor manufacturing process and package carrier | Shih-Hui Wang, Chih-Hung Cheng, Yung-Chi Lin | 2018-03-20 |
| 9899467 | Semiconductor devices, methods of manufacture thereof, and capacitors | Shin-Puu Jeng, Ebin Liao | 2018-02-20 |
| 9893028 | Bond structures and the methods of forming the same | Chen-Hua Yu, Ming-Fa Chen, Yi-Hsiu Chen | 2018-02-13 |
| 9865523 | Robust through-silicon-via structure | Yung-Chi Lin, Tsang-Jiuh Wu | 2018-01-09 |
| 9847256 | Methods for forming a device having a capped through-substrate via structure | Yung-Chi Lin, Yen-Hung Chen, Yin Chen, Ebin Liao, Ku-Feng Yang +1 more | 2017-12-19 |
| 9842823 | Chip-stacking apparatus having a transport device configured to transport a chip onto a substrate | Chen-Hua Yu, HsiaoYun Lo, Yi-Hsiu Chen | 2017-12-12 |
| 9831177 | Through via structure | Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu | 2017-11-28 |
| 9806062 | Methods of packaging semiconductor devices and packaged semiconductor devices | Shin-Puu Jeng, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang | 2017-10-31 |
| 9799694 | Backside through vias in a bonded structure | Weng-Jin Wu, Ku-Feng Yang, Hung-Pin Chang, Chen-Hua Yu | 2017-10-24 |
| 9793192 | Formation of through via before contact processing | Chen-Hua Yu, Weng-Jin Wu | 2017-10-17 |
| 9786580 | Self-alignment for redistribution layer | Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai +2 more | 2017-10-10 |
| 9773768 | Method and structure of three-dimensional chip stacking | Chen-Hua Yu, Yung-Chi Lin | 2017-09-26 |
| 9773701 | Methods of making integrated circuits including conductive structures through substrates | Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen +1 more | 2017-09-26 |