Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183696 | Semiconductor device including bonding pad metal layer structure | Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel +2 more | 2024-12-31 |
| 11764176 | Semiconductor device including bonding pad metal layer structure | Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel +2 more | 2023-09-19 |
| 11329126 | Method of manufacturing a superjunction semiconductor device | Armin Tilke, Hans Weber, Christian Fachmann, Roman Knoefler, Gabor Mezoesi +3 more | 2022-05-10 |
| 6960523 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Michael Maldei, Prakash Dev, David M. Dobuzinsky, Johnathan E. Faltermeier, Chienfan Yu +3 more | 2005-11-01 |
| 6699750 | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips | — | 2004-03-02 |
| 6486505 | Semiconductor contact and method of forming the same | Jeffrey P. Gambino, Peter D. Hoh, Senthil Srinivasan | 2002-11-26 |
| 6444531 | Disposable spacer technology for device tailoring | Scott D. Halle | 2002-09-03 |
| 6291335 | Locally folded split level bitline wiring | Rainer Florian Schnabel, Ulrike Gruening, Gerhard Mueller | 2001-09-18 |
| 6274440 | Manufacturing of cavity fuses on gate conductor level | Kenneth C. Arndt, Axel Brintzinger, Richard A. Conti, Donna R. Cote, Chandrasekhar Narayan +2 more | 2001-08-14 |
| 6268293 | Method of forming wires on an integrated circuit chip | Lawrence A. Clevenger, Greg Costrini, Dave Dobuzinsky, Yoichi Otani, Viraj Y. Sardesai | 2001-07-31 |
| 6258659 | Embedded vertical DRAM cells and dual workfunction logic gates | Ulrike Gruening, Ramachandra Divakaruni, Jack A. Mandelman | 2001-07-10 |
| 6255158 | Process of manufacturing a vertical dynamic random access memory device | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Jack A. Mandelman, Carl Radens | 2001-07-03 |
| 6210995 | Method for manufacturing fusible links in a semiconductor device | Axel Brintzinger, Jeffrey P. Gambino, Scott D. Halle | 2001-04-03 |
| 6204187 | Contact and deep trench patterning | Alan E. Thomas, Franz Zach | 2001-03-20 |
| 6172390 | Semiconductor device with vertical transistor and buried word line | Johann Alsmeier | 2001-01-09 |
| 6153902 | Vertical DRAM cell with wordline self-aligned to storage trench | Toshiharu Furukawa, Ulrike Gruening, David V. Horak, Jack A. Mandelman, Carl Radens | 2000-11-28 |
| 6096664 | Method of manufacturing semiconductor structures including a pair of MOSFETs | Stephan Kudelka, Jeffrey P. Gambino, Mary E. Weybright | 2000-08-01 |
| 6091094 | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips | — | 2000-07-18 |