Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12029041 | Method of forming high-voltage transistor with thin gate poly | Chun Chen, James Pak, Unsoon Kim, Sung-Taeg Kang, Kuo-Tung Chang | 2024-07-02 |
| 11690227 | Method of forming high-voltage transistor with thin gate poly | Chun Chen, James Pak, Unsoon Kim, Sung-Taeg Kang, Kuo-Tung Chang | 2023-06-27 |
| 10872898 | Embedded non-volatile memory device and fabrication method of the same | Chun Chen, James Pak, Unsoon Kim, Sung-Taeg Kang, Kuo-Tung Chang | 2020-12-22 |
| 10497710 | Split-gate flash cell formed on recessed substrate | Sung-Taeg Kang, James Pak, Unsoon Kim, Chun Chen, Kuo-Tung Chang | 2019-12-03 |
| 10242996 | Method of forming high-voltage transistor with thin gate poly | Chun Chen, James Pak, Unsoon Kim, Sung-Taeg Kang, Kuo-Tung Chang | 2019-03-26 |
| 9853039 | Split-gate flash cell formed on recessed substrate | Sung-Taeg Kang, James Pak, Unsoon Kim, Chun Chen, Kuo-Tung Chang | 2017-12-26 |
| 8987092 | Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges | Gang Xue, Shenqing Fang, Rinji Sugino, Yi Ma | 2015-03-24 |
| 8742496 | Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same | Shenqing Fang, Gang Xue, Wenmei Li | 2014-06-03 |
| 8637918 | Method and device employing polysilicon scaling | Shenqing Fang, Chun Chen, Wenmei Li, Gang Xue, Hyesook Hong | 2014-01-28 |
| 8551858 | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory | Shenqing Fang, Angela T. Hui, Shao-Yu Ting, Gang Xue | 2013-10-08 |
| 8487373 | SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same | Shenqing Fang, Gang Xue, Wenmei Li | 2013-07-16 |
| 8076199 | Method and device employing polysilicon scaling | Shenqing Fang, Chun Chen, Wenmei Li, Gang Xue, Hyesook Hong | 2011-12-13 |
| 8026169 | Cu annealing for improved data retention in flash memory devices | Lu You, Alexander H. Nickel, Minh Quoc Tran, Minh Van Ngo, Hieu Pham +4 more | 2011-09-27 |
| 7288487 | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure | Hiroyuki Kinoshita, Calvin T. Gabriel | 2007-10-30 |
| 7242102 | Bond pad structure for copper metallization having increased reliability and method for fabricating same | Hiroyuki Kinoshita, Boon Yong Ang, Hajime Wada, Simon S. Chan, Cinti X. Chen | 2007-07-10 |
| 7122465 | Method for achieving increased control over interconnect line thickness across a wafer and between wafers | Boon Yong Ang, Cinti X. Chen, Simon S. Chan | 2006-10-17 |
| 7060564 | Memory device and method of simultaneous fabrication of core and periphery of same | Hiroyuki Kinoshita, Weidong Qian, Kelwin Ko, Yu Sun | 2006-06-13 |
| 7033957 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Hidehiko Shiraiwa, Tazrien Kamal, Mark T. Ramsbey, Jaeyong Park, Rinji Sugino +4 more | 2006-04-25 |
| 6974989 | Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing | Cinti X. Chen, Boon Yong Ang, Hajime Wada, Sameer Haddad | 2005-12-13 |
| 6969886 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Tazrien Kamal +1 more | 2005-11-29 |
| 6963108 | Recessed channel | Hiroyuki Kinoshita, Jeff P. Erhardt, Emmanuil H. Lingunis | 2005-11-08 |
| 6803275 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Tazrien Kamal +1 more | 2004-10-12 |