Issued Patents All Time
Showing 25 most recent of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400871 | Metal lines with low via-to-via spacing | Daniel James Dechene, Somnath Ghosh, Carl Radens, Lawrence A. Clevenger | 2025-08-26 |
| 12402329 | Top via containing random-access memory cross-bar array | Koichi Motoyama, Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang | 2025-08-26 |
| 12374615 | Electronic devices with a low dielectric constant | Su Chen Fan, Dechao Guo, Carl Radens, Indira Seshadri | 2025-07-29 |
| 12369494 | MRAM top electrode structure with liner layer | Koichi Motoyama, Chanro Park, Yann Mignot, Chih-Chao Yang | 2025-07-22 |
| 12243770 | Hard mask removal without damaging top epitaxial layer | Chanro Park, Yann Mignot, Daniel J. Vincent, Su Chen Fan, Christopher J. Waskiewicz | 2025-03-04 |
| 12148617 | Structure and method to pattern pitch lines | Chanro Park, Chi-Chun Liu, Stuart A. Sieg, Yann Mignot, Koichi Motoyama | 2024-11-19 |
| 12142562 | Subtractive metal etch with improved isolation for BEOL interconnect and cross point | Yann Mignot, Chanro Park | 2024-11-12 |
| 12142556 | X-ray shielding structure for a chip | Yann Mignot, Mary Claire Silvestre, Effendi Leobandung | 2024-11-12 |
| 12113013 | Dual color via patterning | Yann Mignot, Su Chen Fan, Mary Claire Silvestre, Chi-Chun Liu, Junli Wang | 2024-10-08 |
| 12094774 | Back-end-of-line single damascene top via spacer defined by pillar mandrels | Yann Mignot, Yongan Xu | 2024-09-17 |
| 12062609 | Electronic fuse structure embedded in top via | Koichi Motoyama, Chanro Park, Chih-Chao Yang | 2024-08-13 |
| 12010930 | Wrap-around projection liner for AI device | Injo Ok, Mary Claire Silvestre, Yann Mignot | 2024-06-11 |
| 11977614 | Circuit design watermarking | Carl Radens, Lawrence A. Clevenger, Daniel James Dechene | 2024-05-07 |
| 11923246 | Via CD controllable top via structure | Koichi Motoyama, Dominik Metzler, Ekmini Anuja De Silva, Chanro Park | 2024-03-05 |
| 11908732 | Alternating spacers for pitch structure | Chanro Park, Koichi Motoyama | 2024-02-20 |
| 11817389 | Multi-metal interconnects for semiconductor device structures | Chih-Chao Yang, Yann Mignot, Shanti Pancharatnam | 2023-11-14 |
| 11798842 | Line formation with cut-first tip definition | Chanro Park, Koichi Motoyama, Yann Mignot | 2023-10-24 |
| 11784120 | Metal via structure | Yann Mignot, James J. Kelly, Muthumanickam Sankarapandian, Yongan Xu, Daniel J. Vincent | 2023-10-10 |
| 11715594 | Vertically-stacked interdigitated metal-insulator-metal capacitor for sub-20 nm pitch | Chih-Chao Yang | 2023-08-01 |
| 11670580 | Subtractive via etch for MIMCAP | Yann Mignot, Junli Wang, Mary Claire Silvestre, Chi-Chun Liu | 2023-06-06 |
| 11600325 | Non volatile resistive memory logic device | Mary Claire Silvestre, Soon-Cheon Seo, Chi-Chun Liu, Fee Li Lie, Chih-Chao Yang +2 more | 2023-03-07 |
| 11600519 | Skip-via proximity interconnect | Yann Mignot | 2023-03-07 |
| 11569134 | Wafer backside engineering for wafer stress control | Nikhil Jain, Mary Claire Silvestre, Hosadurga Shobha | 2023-01-31 |
| 11489111 | Reversible resistive memory logic gate device | Junli Wang, Su Chen Fan | 2022-11-01 |
| 11417525 | Multiple patterning with mandrel cuts defined by block masks | Martin O'Toole, Keith Donegan, Brendan O'Brien, Terry A. Spooner, Craig Child +4 more | 2022-08-16 |