Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11158633 | Multi-level isolation structure | Haiting Wang, Sipeng Gu, Shesh Mani Pandey, Lixia Lei | 2021-10-26 |
| 10733354 | System and method employing three-dimensional (3D) emulation of in-kerf optical macros | Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung +2 more | 2020-08-04 |
| 10177154 | Structure and method to prevent EPI short between trenches in FinFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Byeong Y. Kim +5 more | 2019-01-08 |
| 9818741 | Structure and method to prevent EPI short between trenches in FINFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Byeong Y. Kim +5 more | 2017-11-14 |
| 9577068 | Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation | Ravikumar Ramachandran, Reinaldo Vega, Richard S. Wise | 2017-02-21 |
| 9431395 | Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation | Ravikumar Ramachandran, Reinaldo Vega, Richard S. Wise | 2016-08-30 |
| 8563398 | Electrically conductive path forming below barrier oxide layer and integrated circuit | Ramachandra Divakaruni, Jeffrey P. Gambino, Randy W. Mann | 2013-10-22 |
| 8039888 | Conductive spacers for semiconductor devices and methods of forming | Gary B. Bronner, David M. Fried, Jeffrey P. Gambino, Leland Chang, Ramachandra Divakaruni +2 more | 2011-10-18 |
| 8008095 | Methods for fabricating contacts to pillar structures in integrated circuits | Solomon Assefa, Christopher V. Jahnes, Michael J. Rooks, Jonathan Zanhong Sun | 2011-08-30 |
| 7923840 | Electrically conductive path forming below barrier oxide layer and integrated circuit | Ramachandra Divakaruni, Jeffrey P. Gambino, Randy W. Mann | 2011-04-12 |
| 7884396 | Method and structure for self-aligned device contacts | David M. Fried | 2011-02-08 |
| 7875550 | Method and structure for self-aligned device contacts | David M. Fried | 2011-01-25 |
| 7871893 | Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices | David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard S. Wise | 2011-01-18 |
| 7605447 | Highly manufacturable SRAM cells in substrates with hybrid crystal orientation | Bruce B. Doris, Oleg Gluschenkov, Meikei Ieong, Nakgeuon Seong | 2009-10-20 |
| 7470615 | Semiconductor structure with self-aligned device contacts | David M. Fried | 2008-12-30 |
| 7374952 | Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof | Ihar Kasko, Sivananda K. Kanakasabapathy | 2008-05-20 |
| 7097777 | Magnetic switching device | John P. Hummel, George Stojakovic, Kia-Seng Low | 2006-08-29 |
| 7001783 | Mask schemes for patterning magnetic tunnel junctions | Frank Findeis, Gill Yong Lee, Chanro Park | 2006-02-21 |
| 6985384 | Spacer integration scheme in MRAM technology | John P. Hummel, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg | 2006-01-10 |
| 6974770 | Self-aligned mask to reduce cell layout area | Kia-Seng Low, David L. Rath, Michael C. Gaidis, Walter Glashauser | 2005-12-13 |
| 6812141 | Recessed metal lines for protective enclosure in integrated circuits | Michael C. Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene J. O'Sullivan, Stephen L. Brown +2 more | 2004-11-02 |
| 6743642 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology | John P. Hummel, Kia-Seng Low, Mahadevaiyer Krishnan | 2004-06-01 |
| 6686296 | Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing | Peter D. Hoh, Richard Wise, Wendy Yan | 2004-02-03 |
| 6680500 | Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers | Kia-Seng Low, John P. Hummel, Igor Kasko | 2004-01-20 |
| 6333559 | Method/structure for creating aluminum wirebound pad on copper BEOL | Ronald D. Goldblatt, John E. Heidenreich, III, Thomas L. McDevitt | 2001-12-25 |